Abstract: A PLL device includes a VCO (10) forming a phase-locked loop and an amplifier (18) for outputting a phase change signal having phase function with respect to frequencies, a synthesizer (20) having a first input receiving an error signal (phase comparison signal) from a phase comparator (2) through an LPF (4) and a second input for synthesizing signals at the first and second inputs to output a synthetic signal, and a phase and amplitude changer (15) for changing the phase and amplitude of the synthetic signal to provide a phase and amplitude change signal to the second input of the synthesizer in response to the error signal, the synthetic signal acting as an oscillation signal of the VCO (10), whereby the PLL device has a small variation in free-running frequency and a wide lock range.

Abstract: In addition to a Gilbert amplifier 101 which includes transistors 1 to 4, a current mirror circuit 102 is disposed. The internal structure of a current supply block 103 is modified. The current supply block 103 linearly converts an externally supplied control voltage Vcont by linear voltage/current conversion and determines a collector current (of a current amount IB) of a transistor 47. The same amount (=IB) of current as this collector current is developed as a collector current of a transistor 42 of the current mirror circuit 102. A collector of the transistor 42 is connected to a current source 45 of the current supply block 103 and an emitter of the transistor 3. Hence, assuming that a current value of the current source 45 is Io, an emitter current IA flowing through the transistor 3 is determined as IA=Io-IB. As a result, an output current I1 of the transistor 1 which has its base connected to the emitter of the transistor 3 changes in proportion to the control voltage Vcont.

Abstract: A first PLL circuit receives a color burst signal of a carrier chrominance signal and outputs a first continuous wave signal which is identical in frequency and phase to the color burst signal. The first continuous wave signal is frequency converted by a first frequency divider and a second PLL circuit into a second continuous wave signal having a frequency of the sum of or difference between frequencies of the carrier chrominance signal and a derived low-frequency conversion chrominance signal. A multiplier multiplies the carrier chrominance signal by the second continuous wave signal. An output signal from the multiplier is supplied to an extraction circuit to obtain the low-frequency conversion chrominance signal.

Abstract: A semiconductor integrated circuit contains a plurality of electronic circuit portions formed thereon, each of which includes an earth wiring. Mutual interference between the circuit portions is reduced by connecting the earth wirings to a common earth electrode, and connecting only a part of the earth wirings to an earth point of the semiconductor substrate.