Patents by Inventor Hiromu ARISAKA
Hiromu ARISAKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735098Abstract: A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.Type: GrantFiled: November 3, 2016Date of Patent: August 15, 2017Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Akio Rokugawa
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Publication number: 20170141023Abstract: A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.Type: ApplicationFiled: November 3, 2016Publication date: May 18, 2017Inventors: HIROMU ARISAKA, NORIYOSHI SHIMIZU, AKIO ROKUGAWA
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Patent number: 9620446Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.Type: GrantFiled: December 8, 2015Date of Patent: April 11, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Noriyoshi Shimizu, Hiromu Arisaka, Akio Rokugawa, Toshinori Koyama
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Patent number: 9565775Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.Type: GrantFiled: August 27, 2014Date of Patent: February 7, 2017Assignee: Shinko Electric Industries Co., Ltd.Inventors: Noriyoshi Shimizu, Wataru Kaneda, Hiromu Arisaka, Akio Rokugawa
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Patent number: 9545016Abstract: A wiring substrate includes an insulating layer, and a connection terminal formed on the insulating layer. The connection terminal includes a metal layer formed on the insulating layer and including an upper surface, a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and a surface plating layer that covers the upper and side surfaces of the metal post. The metal layer includes a material that is inactive with respect to a material included in the surface plating layer. The metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view. The surface plating layer is formed to expose the upper surface edge part of the metal layer.Type: GrantFiled: April 1, 2015Date of Patent: January 10, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Imafuji, Noriyoshi Shimizu, Kiyoshi Ol, Hiromu Arisaka
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Patent number: 9520352Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.Type: GrantFiled: December 8, 2015Date of Patent: December 13, 2016Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
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Publication number: 20160174379Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.Type: ApplicationFiled: December 8, 2015Publication date: June 16, 2016Inventors: Noriyoshi Shimizu, Hiromu Arisaka, Akio Rokugawa, Toshinori Koyama
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Publication number: 20160172287Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.Type: ApplicationFiled: December 8, 2015Publication date: June 16, 2016Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
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Patent number: 9257386Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.Type: GrantFiled: November 20, 2014Date of Patent: February 9, 2016Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Masato Tanaka, Tetsuya Koyama, Akio Rokugawa
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Publication number: 20150305153Abstract: A wiring substrate includes an insulating layer, and a connection terminal formed on the insulating layer. The connection terminal includes a metal layer formed on the insulating layer and including an upper surface, a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and a surface plating layer that covers the upper and side surfaces of the metal post. The metal layer includes a material that is inactive with respect to a material included in the surface plating layer. The metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view. The surface plating layer is formed to expose the upper surface edge part of the metal layer.Type: ApplicationFiled: April 1, 2015Publication date: October 22, 2015Inventors: Kei IMAFUJI, Noriyoshi SHIMIZU, Kiyoshi OI, Hiromu ARISAKA
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Publication number: 20150179560Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.Type: ApplicationFiled: November 20, 2014Publication date: June 25, 2015Inventors: Hiromu Arisaka, Noriyoshi SHIMIZU, Masato TANAKA, Tetsuya KOYAMA, Akio ROKUGAWA
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Publication number: 20150062851Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.Type: ApplicationFiled: August 27, 2014Publication date: March 5, 2015Inventors: Noriyoshi SHIMIZU, Wataru KANEDA, Hiromu ARISAKA, Akio ROKUGAWA