Abstract: An image processor according to the present disclosure includes: a multiplier that receives image data from a pixel section including pixels of a plurality of colors and multiplies the image data by an adjustment parameter that adjusts a color level in each of the pixels; an adjuster that calculates a ratio of respective colors in each of the pixels in the image data and adjusts a value of the adjustment parameter on the basis of the ratio of the respective colors; and a binarization processor that extracts a target image of a specific color on the basis of the image data multiplied by the adjustment parameter.

Abstract: The present disclosure relates to an arithmetic device that reduces a scale of an arithmetic processing unit which performs an arithmetic process between frames in a sensor. A frame memory stores pixel data of a frame that transitions in time sequence. An inter-frame arithmetic processing unit implements a predetermined arithmetic by column parallel in a row unit on the pixel data of a current frame and the pixel data of a past frame stored in the frame memory and updates the pixel data of the past frame stored in the frame memory on the basis of a result of the predetermined arithmetic.

Abstract: To perform inter-pixel image processing with lower latency and higher speed. An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: To perform inter-pixel image processing with lower latency and higher speed. An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: [Object] To reduce a scale of an arithmetic processing unit which performs an arithmetic process between frames in a sensor. [Solution] A frame memory stores pixel data of a frame that transitions in time sequence. An inter-frame arithmetic processing unit implements a predetermined arithmetic by column parallel in a row unit on the pixel data of a current frame and the pixel data of a past frame stored in the frame memory and updates the pixel data of the past frame stored in the frame memory on the basis of a result of the predetermined arithmetic.

Abstract: An image processor according to the present disclosure includes: a multiplier that receives image data from a pixel section including pixels of a plurality of colors and multiplies the image data by an adjustment parameter that adjusts a color level in each of the pixels; an adjuster that calculates a ratio of respective colors in each of the pixels in the image data and adjusts a value of the adjustment parameter on the basis of the ratio of the respective colors; and a binarization processor that extracts a target image of a specific color on the basis of the image data multiplied by the adjustment parameter.

Abstract: A digital recording/reproduction method and apparatus includes a data detection circuit for detecting a frequency of occurrence of a specific data value contained in an information signal, and a phase controller for controlling a phase of a sampling clock based on the frequency of occurrence of the specific data value detected by the data detection circuit. A threshold value in the data detection circuit is adjusted to maximize the frequency of occurrence of the specific data value contained in the information signal, and the phase of the sampling clock is controlled to minimize the amount of change in the frequency of occurrence of the specific data value contained in the information signal.

Abstract: The waveform equalizer comprises equalizing means for equalizing the waveform of the reproduction signal based on the equalizing coefficient, reference signal-generating means for extracting an isolated wave from the reproduction signal to generate a reference signal based on the isolated wave and equalizing coefficient control means for carrying out an operation of the equalizing error of the isolated wave of the reproduction signal whose waveform has been equalized by the equalizing means from the reference signal, to control the equalizing coefficient based on the equalizing error, wherein the reference signal is generated based on the reproduction signal, and the equalizing coefficient is determined in response to the reproduction signal using this reference signal.

Abstract: A digitally recording and reproducing apparatus simultaneously records two kinds of digital signals of an identical video program, generated by high-efficiency coding, or a relatively high bit-rate signal and a relatively low bit-rate signal, onto the approximately the same positions on the tape. The apparatus is constructed so that the low bit-rate signal is commonly used for normal playback and search-playback. Further, the recording time can be lengthened by reducing the recording bit-rate.

Abstract: A digital recording and reproducing apparatus records two kinds of digital signals of an identical video program, generated by high-efficiency coding, or a relatively high bit-rate signal and a relatively low bit-rate signal, onto approximately the same positions on the tape. When the low bit-rate signal is commonly used for normal playback and search-playback or when it is used only for the search-playback, the amount of the search-playback data is adjusted so that data on a number of frames to be a unit for edit work may be recorded onto an integer number of tracks.

Abstract: A digital VTR which is able to record a band-compressed signal having a bit-rate of 17 to 60 Mbps of a program while creating a low-bit-rate signal (1.5 to 5 Mbps) having the same program content as well as utilizing the low-bit-rate signal as a signal for the special playback. Variable speed playback data for a certain speed, which is recorded in the limited recording areas for variable-speed playback mode, is adapted to be used for playback at another speed in the variable-speed playback mode. The data structure of variable-speed playback data is adapted to change depending on the image areas on the image frame. Either of these embodiments or the combination of them, improves the quality of a reproduced picture during variable-speed playback mode in which a less amount of data is available than that of data read out at the time of a normal playback mode.

Abstract: A magnetic recording and reproducing apparatus which includes a set of loading members for drawing out a magnetic tape accommodated in a tape cassette and wound around a set of reels disposed to contact the same plane. The tape storing portions of the tape cassette are directed along part of the outer peripheral surface of a rotary head cylinder in an approximately M-shape, and a single inclining member is provided in the vicinity of one tape storing portion for causing a tape travelling reference face of the magnetic tape drawn out from the tape storing portion to be inclined.

Abstract: In a helical-scan magnetic record/playback system, n magnetic heads (where n is an integer greater than one) are disposed close to the outer wall of a head drum, spaced from one another by 2.pi./n radians with respect to the rotational axis of the head drum and also spaced from one another by approximately 1/n of the width of a magnetic tape in the axial direction of the head drum. The magnetic tape is wound around the head drum over an angle of 2.pi./n radians or more with respect to the rotational axis of the drum. With the rotation of the head drum, a video signal is time-sequentially divided for recording on n tracks of the tape and for reproduction therefrom. The invention results in reduced friction between the tape and the drum, thereby providing smooth travel and easy loading of the tape. According to this invention, a still or slow-motion picture can be reproduced without an external memory and the reciprocal travel of the tape.

Abstract: In a digital magnetic recording and reproducing apparatus, a digital code signal to be recorded is given a code conversion by means of modulo-2-adding another digital signal thereto to prevent a continuation of the same binary signal levels for a prolonged period. The signal level of the reproduced digital code signal is corrected by level comparison with a threshold level provided by applying the above reproduced digital code signal to a compensator and peak rectifiers, which have the same time-constant, and then the reproduced digital code signal is given another code conversion by means of modulo-2-adding still another digital signal provided for restoring the code conversion, so that it is possible to reproduce the original digital code signal faithfully.

Abstract: A hybrid servo control system for controlling, for example a rotation of a capstan driving motor or a head motor of a video tape recorder comprises at least an integral control loop including an analog phase comparator for detecting in an analog mode a phase difference between a signal related to the rotation of the capstan driving motor or the head motor to be controlled and a reference signal so as to produce an analog amount corresponding to said phase difference, an analog-digital converter for converting said analog amount into a digital amount and a digital frequency modulator for frequency modulating in a digital mode clock pulses with said digital amount.