Patents by Inventor Hironori KAWAMINAMI

Hironori KAWAMINAMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438933
    Abstract: A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first semiconductor die includes buffers in a second-stage configuration to an Nth-stage configuration (N being an integer of 3 or more) in a clock tree structure, and the second semiconductor die includes a logic circuit electrically connected to the buffer in the Nth-stage configuration.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 8, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Kawaminami
  • Patent number: 10418315
    Abstract: A semiconductor device includes: a first semiconductor chip that includes through electrodes; a second semiconductor chip; and an interposer that has a recessed portion formed in a front surface thereof and includes a first wiring provided under a bottom surface of the recessed portion, in which the first semiconductor chip is fitted in the recessed portion with a chip top surface thereof flipped down to be electrically connected to the first wiring, the second semiconductor chip is connected on the front surface, of the interposer, around the recessed portion, and at the same time, is stacked on the first semiconductor chip in a manner to partially overlap the first semiconductor chip, and is electrically connected to the first semiconductor chip via the through electrodes.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Kawaminami
  • Publication number: 20180308826
    Abstract: A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first semiconductor die includes buffers in a second-stage configuration to an Nth-stage configuration (N being an integer of 3 or more) in a clock tree structure, and the second semiconductor die includes a logic circuit electrically connected to the buffer in the Nth-stage configuration.
    Type: Application
    Filed: March 21, 2018
    Publication date: October 25, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Hironori KAWAMINAMI
  • Patent number: 10103124
    Abstract: A semiconductor device includes a first semiconductor chip including plural circuit blocks provided on a semiconductor substrate, and plural through-silicon vias that are arranged so as to surround the outer periphery of each of the plural circuit blocks and that penetrate the semiconductor substrate, and a second semiconductor chip that is stacked on the first semiconductor chip, and that is supplied with a power source through the plural through-silicon vias.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: October 16, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Kawaminami
  • Publication number: 20180294215
    Abstract: A semiconductor device includes: a first semiconductor chip that includes through electrodes; a second semiconductor chip; and an interposer that has a recessed portion formed in a front surface thereof and includes a first wiring provided under a bottom surface of the recessed portion, in which the first semiconductor chip is fitted in the recessed portion with a chip top surface thereof flipped down to be electrically connected to the first wiring, the second semiconductor chip is connected on the front surface, of the interposer, around the recessed portion, and at the same time, is stacked on the first semiconductor chip in a manner to partially overlap the first semiconductor chip, and is electrically connected to the first semiconductor chip via the through electrodes.
    Type: Application
    Filed: March 21, 2018
    Publication date: October 11, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Hironori KAWAMINAMI
  • Patent number: 9691740
    Abstract: A semiconductor device includes: a plurality of semiconductor chips which are stacked; a plurality of circuit blocks respectively included in the plurality of semiconductor chips; a first power supply domain that supplies power and stops the supply of the power to one of the plurality of circuit blocks independently of the other circuit blocks; and a second power supply domain that supplies power and stops the supply of the power to at least two of the plurality of circuit blocks in common and supplies the power and stops the supply of the power independently of the other circuit blocks.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Akihiro Chiyonobu, Hironori Kawaminami
  • Publication number: 20170053900
    Abstract: A semiconductor device includes a first semiconductor chip including plural circuit blocks provided on a semiconductor substrate, and plural through-silicon vias that are arranged so as to surround the outer periphery of each of the plural circuit blocks and that penetrate the semiconductor substrate, and a second semiconductor chip that is stacked on the first semiconductor chip, and that is supplied with a power source through the plural through-silicon vias.
    Type: Application
    Filed: July 15, 2016
    Publication date: February 23, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hironori KAWAMINAMI
  • Publication number: 20170026036
    Abstract: A semiconductor device includes: a plurality of semiconductor chips which are stacked; a plurality of circuit blocks respectively included in the plurality of semiconductor chips; a first power supply domain that supplies power and stops the supply of the power to one of the plurality of circuit blocks independently of the other circuit blocks; and a second power supply domain that supplies power and stops the supply of the power to at least two of the plurality of circuit blocks in common and supplies the power and stops the supply of the power independently of the other circuit blocks.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 26, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Akihiro Chiyonobu, Hironori KAWAMINAMI