Patents by Inventor Hironori Maruyama
Hironori Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240181690Abstract: Provided is an injection molding control device with which an operator can simply change display content. An injection molding control device according to an aspect of the present disclosure is an injection molding control device, which controls an injection molding operation of an injection molding machine, comprising: a touch panel; a storage unit which stores data collected in the injection molding machine; and a display control unit which displays, on the touch panel, a graph of a portion of the data extracted from the storage unit, and changes display content of the graph in response to a touch operation on the touch panel, wherein the display control unit changes display content of the graph to different content according to a case where the touch operation is a prescribed gesture operation through a single touch and a case where the touch operation is the gesture operation through multiple touches.Type: ApplicationFiled: June 17, 2021Publication date: June 6, 2024Applicant: FANUC CORPORATIONInventors: Hironori KUSAKABE, Junpei MARUYAMA, Masaya TAJIKA
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Patent number: 8893865Abstract: The impact absorbing structure of the present invention is an impact absorbing structure for absorbing an impact in a case where the impact absorbing structure is subjected to the impact in a predetermined direction. The impact absorbing structure comprises a plurality of impact absorbing members, each of which is a tubular-shaped body whose longitudinal central axis is arranged along the impact direction and capable of absorbing the impact by being compressively collapsed when receiving the impact from the impact direction. At least one of the plurality of impact absorbing members being placed in such a way that a front end of the impact absorbing members is placed at a different position of ends of the other impact absorbing members in the impact direction, and the front end is an end closer to the direction which is forward in the impact direction.Type: GrantFiled: January 31, 2011Date of Patent: November 25, 2014Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Atsumi Tanaka, Hironori Maruyama, Naoki Higuchi
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Patent number: 8813926Abstract: An object is to provide an impact-absorbing structure superior in impact-absorbing capacity. An impact-absorbing structure includes a pair of flat, plate-like face plates arranged to oppose each other with a predetermined distance therebetween; a core member arranged between the face plates and fixed to the face plates; and a composite-material tube arranged between the face plates, at the core member side, the impact-absorbing member extending in one direction and fracturing progressively due to an impact compression force acting in the one direction. The composite-material tube is fixed to the face plates at one portion constituting a bonded region and is allowed to move relative to the face plates at a remaining portion constituting a non-bonded region.Type: GrantFiled: April 15, 2010Date of Patent: August 26, 2014Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Atsumi Tanaka, Hironori Maruyama, Masayuki Kanemasu
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Multilayer circuit board, insulating sheet, and semiconductor package using multilayer circuit board
Patent number: 8604352Abstract: Semiconductor chip mounting yield and semiconductor package reliability deteriorate due to warpage of a multilayer circuit board. A multilayer circuit board (1) using an interlayer insulating layer (6) can suppress warpage of the entire multilayer circuit board (1) by making the interlayer insulating layer (6) serve as a buffer material. In the multilayer circuit board (1) using the interlayer insulating layer (6), conductor circuit layers (11) and interlayer insulating layers (6) are alternately arranged. The interlayer insulating layer (6) to be used in the multilayer circuit board (1) includes a first insulating layer and a second insulating layer having an elastic modulus higher than that of the first insulating layer.Type: GrantFiled: March 25, 2009Date of Patent: December 10, 2013Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Hironori Maruyama, Hitoshi Kawaguchi, Hiroyuki Tanaka -
Publication number: 20120187717Abstract: The impact absorbing structure of the present invention is an impact absorbing structure for absorbing an impact in a case where the impact absorbing structure is subjected to the impact in a predetermined direction. The impact absorbing structure comprises a plurality of impact absorbing members, each of which is a tubular-shaped body whose longitudinal central axis is arranged along the impact direction and capable of absorbing the impact by being compressively collapsed when receiving the impact from the impact direction. At least one of the plurality of impact absorbing members being placed in such a way that a front end of the impact absorbing members is placed at a different position of ends of the other impact absorbing members in the impact direction, and the front end is an end closer to the direction which is forward in the impact direction.Type: ApplicationFiled: January 31, 2011Publication date: July 26, 2012Inventors: Atsumi Tanaka, Hironori Maruyama, Naoki Higuchi
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Patent number: 8227703Abstract: A multilayered circuit board of the present invention has a single-side laminated structure and does not include a core substrate having via-holes formed therethrough and vias for providing electrical connection through the via-holes. The multilayered circuit board includes a plurality of pairs of layers, each pair including a conductor circuit layer and an insulator layer, wherein a glass transition temperature of each insulator layer is 170° C. or higher, a coefficient of thermal expansion at the glass transition temperature or lower of each insulator layer is 35 ppm or less, and a modulus of elasticity of each insulator layer is 5 GPa or more.Type: GrantFiled: January 17, 2008Date of Patent: July 24, 2012Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Hironori Maruyama, Kensuke Nakamura, Toru Meura, Hiroshi Hirose
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MULTILAYER CIRCUIT BOARD, INSULATING SHEET, AND SEMICONDUCTOR PACKAGE USING MULTILAYER CIRCUIT BOARD
Publication number: 20110024172Abstract: Semiconductor chip mounting yield and semiconductor package reliability deteriorate due to warpage of a multilayer circuit board. A multilayer circuit board (1) using an interlayer insulating layer (6) can suppress warpage of the entire multilayer circuit board (1) by making the interlayer insulating layer (6) serve as a buffer material. In the multilayer circuit board (1) using the interlayer insulating layer (6), conductor circuit layers (11) and interlayer insulating layers (6) are alternately arranged. The interlayer insulating layer (6) to be used in the multilayer circuit board (1) includes a first insulating layer and a second insulating layer having an elastic modulus higher than that of the first insulating layer.Type: ApplicationFiled: March 25, 2009Publication date: February 3, 2011Applicant: Sumitomo Bakelite Co., Ltd.Inventors: Hironori Maruyama, Hitoshi Kawaguchi, Hiroyuki Tanaka -
Publication number: 20100263976Abstract: An object is to provide an impact-absorbing structure superior in impact-absorbing capacity. An impact-absorbing structure includes a pair of flat, plate-like face plates arranged to oppose each other with a predetermined distance therebetween; a core member arranged between the face plates and fixed to the face plates; and a composite-material tube arranged between the face plates, at the core member side, the impact-absorbing member extending in one direction and fracturing progressively due to an impact compression force acting in the one direction. The composite-material tube is fixed to the face plates at one portion constituting a bonded region and is allowed to move relative to the face plates at a remaining portion constituting a non-bonded region B.Type: ApplicationFiled: April 15, 2010Publication date: October 21, 2010Inventors: Atsumi TANAKA, Hironori Maruyama, Masayuki Kanemasu
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Publication number: 20100025093Abstract: A multilayered circuit board of the present invention has a single-side laminated structure and does not include a core substrate having via-holes formed therethrough and vias for providing electrical connection through the via-holes. The multilayered circuit board includes a plurality of pairs of layers, each pair including a conductor circuit layer and an insulator layer, wherein a glass transition temperature of each insulator layer is 170° C. or higher, a coefficient of thermal expansion at the glass transition temperature or lower of each insulator layer is 35 ppm or less, and a modulus of elasticity of each insulator layer is 5 GPa or more.Type: ApplicationFiled: January 17, 2008Publication date: February 4, 2010Applicant: Sumitomo Bakelite Company LimitedInventors: Hironori Maruyama, Kensuke Nakamura, Toru Meura, Hiroshi Hirose
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Patent number: 5314773Abstract: Black toner for electrophotography used for visualizing an electrostatic latent image formed on an image-holding body is provided which includes a resin binder and carbon black dispersed in the resin binder. The carbon black has a volatile component content of 4% or more, a structure index of 100 or more, and a mean grain size in the range of 20 to 35 nm.Type: GrantFiled: July 6, 1992Date of Patent: May 24, 1994Assignee: Mita Industrial Co., Ltd.Inventors: Masahiko Kubo, Akihiro Watanabe, Takafumi Nagai, Hironori Maruyama
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Patent number: 5239342Abstract: The present invention provides a developing method which comprises transferring a two-component developer comprising a magnetic carrier and a toner from a sleeve to a development area and developing a latent electrostatic image on a latent electrostatic image-carrier in the development area, wherein the development conditions in the development area are prescribed so as to satisfy the formulae (1) and (2):140 .gtoreq.R.times.(S/D).gtoreq.50 (1)andR=M(Wt.times.(1/.rho.t)+Wc.times.(1/.rho.c))/H (2)wherein S is the peripheral speed (cm/sec) of the development sleeve, D is the peripheral speed (cm/sec) of the latent electrostatic image-carrier, M is the coated amount (g/cm.sup.2) of the developer per unit area of the sleeve, H is the distance (cm) at which the sleeve most approaches a drum of a photosensitive material, Wt is the weight concentration (%) of the toner in the developer, Wc is the weight concentration (%) of the carrier in the developer, .rho.t is the true density (g/cm.sup.3) of the toner, and .rho.Type: GrantFiled: June 25, 1992Date of Patent: August 24, 1993Assignee: Mita Industrial Co., Ltd.Inventors: Masahiko Kubo, Akihiro Watanabe, Takafumi Nagai, Hironori Maruyama