Abstract: According to one embodiment, a chopper stabilized amplifier includes an input unit, a first chopper, a first amplifier, and a switch circuit. The input unit receives a differential input signal at a first input terminal and a second input terminal. The first chopper modulates the differential input signal based on a first control signal and an inverse signal of the first control signal. The first amplifier amplifies the signals with the modulated differential output from the first chopper. The switch circuit is provided between the input unit and the first chopper, and receives a second control signal and reduces input currents which flow in the first chopper when the first chopper performs a modulating operation, by using an operation with the second control signal.

Abstract: According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal to two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amounts of attenuation values. In the first conductive element, a first amount of attenuation is set. The high frequency integrated circuit outputs a plurality of output signals having different gain values from the first high frequency output terminal and the second high frequency output terminal, respectively.

Abstract: According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal to two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amounts of attenuation values. In the first conductive element, a first amount of attenuation is set. The high frequency integrated circuit outputs a plurality of output signals having different gain values from the first high frequency output terminal and the second high frequency output terminal, respectively.

Abstract: A variable capacitance circuit has a plurality of series circuits connected in parallel. The plurality of series circuits comprise a plurality of switches having different off-capacitances of powers of two with respect to a reference capacitance, and a plurality of capacitors connected in series to the plurality of switches and having different capacitances of powers of two with respect to a reference capacitance.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an oscillation circuit, a charge pump circuit, a smoothing circuit, and a negative feedback circuit. The charge pump circuit is arranged between each of a power supply input terminal and the oscillation circuit and a power supply output terminal. The smoothing circuit is arranged between the charge pump circuit and the power supply output terminal. The negative feedback circuit is arranged on a path returning from the smoothing circuit to the oscillation circuit. The smoothing circuit includes a first zero point generation circuit.

Abstract: According to one embodiment, a semiconductor device includes: a first circuit transmitting a first signal; a second circuit receiving a second signal; a first level shift circuit converting a signal level of the first signal from a value corresponding to a first voltage to a value corresponding to a second voltage different from the first voltage, and transmitting the second signal; and a third circuit receiving the first signal and a control signal, and transmitting a third signal having a fixed signal level to the first level shift circuit when a signal level of the control signal is a first level.

Abstract: According to one embodiment, a charge pump is configured to generate a negative potential at an output node. A first transistor and a first resistor are coupled in series in order between a first node and a second node. A second resistor is coupled between the second node and the output node. A second transistor and a third resistor are coupled in series in order between the first node and a third node. A fourth resistor is coupled between the third node and the output node. A third transistor is coupled between a fourth node and the output node, and coupled to the second node and the third node at a gate.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an oscillation circuit, a charge pump circuit, a smoothing circuit, and a negative feedback circuit. The charge pump circuit is arranged between each of a power supply input terminal and the oscillation circuit and a power supply output terminal. The smoothing circuit is arranged between the charge pump circuit and the power supply output terminal. The negative feedback circuit is arranged on a path returning from the smoothing circuit to the oscillation circuit. The smoothing circuit includes a first zero point generation circuit.

Abstract: According to one embodiment, a charge pump is configured to generate a negative potential at an output node. A first transistor and a first resistor are coupled in series in order between a first node and a second node. A second resistor is coupled between the second node and the output node. A second transistor and a third resistor are coupled in series in order between the first node and a third node. A fourth resistor is coupled between the third node and the output node. A third transistor is coupled between a fourth node and the output node, and coupled to the second node and the third node at a gate.

Abstract: A semiconductor device according to an embodiment includes; an N-channel type first MOS transistor having a first drain connected to an input terminal, a first source connected to an output terminal, a first gate insulation film, and a first gate; a P-channel type second MOS transistor having a second drain connected to the input terminal in parallel with the first drain, a second source connected to the output terminal in parallel with the first source, a second gate insulation film whose area is larger than an area of the first gate insulation film, and a second gate; an inverter connected to a control terminal in parallel with the first gate; and a delay circuit disposed between the inverter and second gate.

Abstract: A semiconductor device according to an embodiment includes; an N-channel type first MOS transistor having a first drain connected to an input terminal, a first source connected to an output terminal, a first gate insulation film, and a first gate; a P-channel type second MOS transistor having a second drain connected to the input terminal in parallel with the first drain, a second source connected to the output terminal in parallel with the first source, a second gate insulation film whose area is larger than an area of the first gate insulation film, and a second gate; an inverter connected to a control terminal in parallel with the first gate; and a delay circuit disposed between the inverter and second gate.

Abstract: A power-supply voltage sensing circuit includes a switch circuit having an input connected to a power supply and an output connected to a main circuit, a first circuit that outputs a first signal controlling ON/OFF of the switch circuit in accordance with a power-supply voltage supplied by the power supply, a second circuit that delays the first signal and outputs the delayed first signal as a second signal, a first transistor that outputs a first voltage in accordance with the second signal from the second circuit, a third circuit that outputs a reference voltage when supplied with the power-supply voltage, and a comparison circuit that outputs a third signal that controls whether or not the main circuit is operated in accordance with the first voltage and the reference voltage.

Abstract: According to one embodiment, the voltage comparison circuit includes: a first MOS transistor having a first gate applied with a first input voltage, a second MOS transistor having a second gate applied with a second input voltage compared with the first input voltage, a first current source connected in common to sources of the first and second MOS transistors, loads connected to drains of the first and the second MOS transistors, a third MOS transistor having a third gate connected to either one of the drains of the first and second MOS transistors, a logic inverter circuit connected to the drain of the third MOS transistor and generating a logic output based on a voltage difference between the first and second input voltages, and an additional circuit for controlling voltage of the node connected to the drain of the third MOS transistor, the second current source, and the first logic inverter circuit.

Abstract: A power-supply voltage sensing circuit includes a switch circuit having an input connected to a power supply and an output connected to a main circuit, a first circuit that outputs a first signal controlling ON/OFF of the switch circuit in accordance with a power-supply voltage supplied by the power supply, a second circuit that delays the first signal and outputs the delayed first signal as a second signal, a first transistor that outputs a first voltage in accordance with the second signal from the second circuit, a third circuit that outputs a reference voltage when supplied with the power-supply voltage, and a comparison circuit that outputs a third signal that controls whether or not the main circuit is operated in accordance with the first voltage and the reference voltage.

Abstract: A power supply voltage detector circuit includes a control signal terminal, switch circuit, first voltage detector circuit, and second voltage detector circuit. The first voltage detector circuit has a first input connected to a power supply terminal and a first output connected to the control signal input of the switch circuit. The first voltage detector circuit outputs a first-ON signal to a control signal input of the switch circuit when the power supply voltage is greater than or equal to the first threshold. The second voltage detector circuit has a second input connected to a power supply output of the switch circuit and second output connectable to a load circuit. The second voltage detector circuit outputs a second-ON signal to the control signal terminal to activate the load circuit when the voltage at the second input is greater than or equal to the second threshold.

Abstract: A coupler comprises a multi-layer wiring substrate. A signal transmission line of the coupler has a first line portion extending in a first direction within a first wiring layer of the multi-layer wiring substrate. A branch line of the coupler has a parallel portion that extends along the first direction in parallel with the first line portion. The branch line is connected to the signal transmission line through first and second connection portions in a second wiring layer. A coupling line is disposed in a wiring layer of the multi-layer wiring substrate that is not the first wiring layer. The coupling line is vertically adjacent, via an insulating layer of the multi-layer wiring substrate, to the parallel portion of the branch line.

Abstract: A semiconductor switch circuit includes a switch between an input node and an output node that connects nodes to each other according to a control signal and a level shifter outputting the control signal at a boosted level that is greater than a power supply voltage level. The semiconductor switch circuit also includes a booster circuit to output a boosted voltage at the boosted level higher than a power supply voltage level. A control circuit is configured to control the level shifter output of the control signal to the switch. A capacitance switching circuit is included to change the capacitance of a connection between the booster circuit and the level shifter. The capacitance switching circuit can vary capacitance according to the voltage level of the booster circuit output.

Abstract: A semiconductor switch circuit includes a switch between an input node and an output node that connects nodes to each other according to a control signal and a level shifter outputting the control signal at a boosted level that is greater than a power supply voltage level. The semiconductor switch circuit also includes a booster circuit to output a boosted voltage at the boosted level higher than a power supply voltage level. A control circuit is configured to control the level shifter output of the control signal to the switch. A capacitance switching circuit is included to change the capacitance of a connection between the booster circuit and the level shifter. The capacitance switching circuit can vary capacitance according to the voltage level of the booster circuit output.

Abstract: A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.

Abstract: According to one embodiment, a constant voltage power circuit includes a bias generator, a reference voltage generator, and a constant voltage generator, a bias switch, a constant voltage controller. The bias generator generates a first bias voltage. The reference voltage generator is connected to the bias generator and generates a reference voltage. The constant voltage generator generates a constant voltage. The bias switch switches a bias supplied to the constant voltage generator in accordance with a switch control signal controlling the bias switch. The constant voltage controller obtains a detected voltage corresponding to the constant voltage or a power supply voltage, and generates a constant voltage control signal and the switch control signal. The constant voltage control signal sets an operating state of the constant voltage generator to an enable state or a disable state.