Abstract: A semiconductor optical device includes a substrate of a first conductivity type; an optical confinement layer of the first conductivity type, which is arranged above the substrate of the first conductivity type; a multi quantum well layer, which is arranged above the optical confinement layer of the first conductivity type, and comprises a plurality of well layers and a plurality of barrier layers; an optical confinement layer of a second conductivity type, which is arranged on the multi quantum well layer; and a PL stabilization layer, which is arranged between the substrate of the first conductivity type and the multi quantum well layer. The PL stabilization layer having a thickness that is half a thickness of the multi quantum well layer or more, and having a composition wavelength that is shorter than a composition wavelength of the plurality of well layers of the multi quantum well layer.

Abstract: A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface, a first, second, and third sublayer, the first and third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer, and the second sublayer consisting of one or more layers selected from InGaAs, InAlAs, InGaAlAs, InGaAsP, and InAlAsP.

Abstract: A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface of the semiconductor substrate, a first sublayer, a second sublayer, and a third sublayer, the first sublayer, the second sublayer, and the third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer from the surface of the semiconductor substrate, and the second sublayer consisting

Abstract: The object of the present invention is to provide a radar receiver that can steadily and reliably detect the target in the close zone without largely complicating the construction compared to the conventional radar apparatuses. The radar receiver according to the present invention comprises a receiving unit 15 that detects or modulates a received wave for detecting a target, the received wave arriving from the target in response to a transmitting wave transmitted towards the target, and a control unit 19 that sets a gain of the receiving unit 15 to a value at which the receiving unit is prevented from falling into a saturation region by a component of the transmission wave that wraps around the receiving unit 15 through an aerial system used for transmission of the transmission wave during a period in which the transmission wave is being transmitted.

Abstract: A design supporting apparatus of a semiconductor device, includes sections to perform: setting an impurity concentration with respect to a channel direction and a depth direction to node points arranged discretely in a channel region of a model transistor based on a predetermined concentration distribution rule; calculating an electric characteristic of the model transistor by using the impurity concentration; and storing the impurity concentration as a model parameter of the model transistor in a storage unit, when the calculated electric characteristic and an electric characteristic prepared previously are coincident with each other within a predetermined range.

Abstract: An analysis and design apparatus for semiconductor device, which utilizes a transistor model using accurate channel impurity concentration distribution are provided. The analysis and design apparatus includes a parameter setting portion that divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. Further, the analysis and design apparatus includes an element characteristic calculation portion that values of electric characteristics of the transistor using surface potential that is calculated by solving a Poisson equation using a plurality of effective impurity concentrations. Moreover, the determination portion compares the calculated values with measured values read from a storage portion based on the structure information, and determines that the plurality of parameters for the transistor when the measured values correspond to the calculated values.

Abstract: In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other.

Abstract: A semiconductor circuit designing supporting system, includes: a storage unit in which two models of a first model and a second model are stored as device models a semiconductor device; and an operation unit. The operating unit includes: a characteristic variation calculating section configured to calculate a variation of a device characteristic when process parameters are varied by using the first model; and an analyzing section configured to normalize based on the variation, an error between a device characteristic calculated by using the second model and actual measurement data and to analyze the second model by using the normalized error.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A design supporting apparatus of a semiconductor device, includes sections to perform: setting an impurity concentration with respect to a channel direction and a depth direction to node points arranged discretely in a channel region of a model transistor based on a predetermined concentration distribution rule; calculating an electric characteristic of the model transistor by using the impurity concentration; and storing the impurity concentration as a model parameter of the model transistor in a storage unit, when the calculated electric characteristic and an electric characteristic prepared previously are coincident with each other within a predetermined range.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: An analysis and design apparatus for semiconductor device, includes a storage portion, a parameter setting portion, an element characteristic calculation portion, and a determination portion. The storage portion stores structure information and measured values of a transistor. The parameter setting portion divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. The element characteristic calculation portion calculates a plurality of effective impurity concentrations in the plurality of regions based on the plurality of parameters, calculates a surface potential by solving a Poisson equation using the plurality of effective impurity concentrations, and calculates calculated values of electric characteristics of the transistor using the surface potential.

Abstract: In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other, and stores the function in the storage section.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A circuit simulation method for estimating electrical characteristics of a semiconductor device is provided. The circuit simulation method includes: (A) generating a device model parameter of a semiconductor device model used in a circuit simulation; and (B) executing the circuit simulation by using the semiconductor device model and the generated device model parameter. The (A) step includes: (a) generating a plurality of device model parameters with respect to a plurality of different temperatures; and (b) generating the device model parameter corresponding to a specified temperature by interpolating between the plurality of device model parameters.

Abstract: From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

Abstract: From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

Abstract: In a method of extracting parameters of a diffusion model from object parameters to be used in a process simulation of a semiconductor manufacturing process, classifying the object parameters into a first through an N-th (N being a natural integer not smaller than 2) groups, the first group being used for classifying thereinto the most fundamental physical and least model-dependent parameters, the N-th group being used for classifying thereinto the least fundamental physical and most model-dependent parameters, and extracting successively the classified parameters in the first through the N-th groups in the order from the first to the N-th group.

Abstract: In an epoxy resin composition comprising an epoxy resin, a curing agent, and an inorganic filler, the filler is porous silica having a specific surface area of 6-200 m2/g, a true specific gravity of 2.0-2.2, and a mean particle size of 2-50 &mgr;m. The epoxy resin composition is readily moldable, has a low moisture permeability and reliability in the cured state, and is suitable for forming a premolded hollow semiconductor package.