Abstract: A semiconductor device has a semiconductor substrate, an internal circuit formed on the semiconductor substrate, a connection pad formed on the semiconductor substrate and connected to the internal circuit, and a test pad formed on the semiconductor substrate so as to be connected to the connection pad and used for functional testing of the internal circuit. The semiconductor substrate has a bonding region provided on the surface thereof so as to allow another semiconductor substrate to be superposed thereon by being bonded thereto, with the connection pad formed inside the bonding region and the test pad formed outside the bonding region.

Abstract: An integrated circuit device has a first IC chip, a second IC chip, and a circuit board having a hole formed therein that is large enough to permit the second IC chip to be accommodated therein. The first and second IC chips are bonded together so as to be electrically connected together, and the first IC chip is mounted on the circuit board with the second IC chip accommodated in the hole formed in the circuit board. Here, one of the IC chips forming a chip-on-chip structure is accommodated in the hole formed in the circuit board, making further thickness reduction possible. Moreover, the obverse surfaces of the IC chips are located closer to the circuit board, making possible wireless mounting of the IC chips, despite forming a chip-on-chip structure, on the circuit board through connection using bumps. This helps reduce trouble due to inductance in a circuit that handles a high-frequency signal.

Abstract: A semiconductor device is built by combining together a plurality of semiconductor chips, but nevertheless allows easy functional checking of the individual semiconductor chips before they are assembled together without provision of extra pads for such checking.

Abstract: A semiconductor device has a first semiconductor chip and a second semiconductor chip superposed on and bonded to the surface of the first semiconductor chip. In the region on the first semiconductor chip where the second semiconductor chip is bonded thereto, connection pads are arranged in positions that fit a plurality of predetermined types of semiconductor chips. On the second semiconductor chip, connection pads are arranged in positions that fit the connection pads arranged on the first semiconductor chip.

Abstract: A multichip semiconductor device has a first semiconductor chip and a second semiconductor chip superposed on and bonded to each other so as to form a chip-on-chip structure. The first semiconductor chip has a field-programmable gate array circuit and a switch circuit formed thereon. The second semiconductor chip has a non-volatile configuration memory circuit formed thereon for storing the setting information about how to set the circuit of the field-programmable gate array circuit.

Abstract: A semiconductor device is including a first semiconductor chip, and a second semiconductor chip stacked on the first semiconductor chip and bonded to a surface of the first semiconductor chip. The first semiconductor chip and the second semiconductor chip are formed with a first element and a second element, respectively, which are provided in an opposed relation and adapted to be coupled to each other in an electrically isolated state for signal transmission. The first semiconductor chip has an external connector isolated from the first element and electrically connected to the second element. The first semiconductor chip may have a protective circuit for prevention of insulation breakdown between the first element and the second element.

Abstract: A semiconductor chip for use in a semiconductor device of chip-on-chip structure in which a second semiconductor chip is stacked on the semiconductor chip and bonded to a surface of the semiconductor chip. The semiconductor chip includes: chip interconnection portions provided on the surface of the semiconductor chip for electrical connection to the second semiconductor chip; and a shielding conductive portion surrounding the chip interconnection portions and connected to a low impedance portion. The chip interconnection portions may be generally evenly arranged in a bonding surface area of the semiconductor chip onto which the second semiconductor chip is bonded.