Abstract: A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.

Abstract: A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.

Abstract: A power supply device includes a main power supply, a sub-power supply, a main power supply path, a sub-power supply path, a power supply selector switch, and a load selector switch group. The main power supply path is connected to the main power supply. The sub-power supply path is different from the main power supply path and is connected to the sub-power supply. The load selector switch group is disposed between the main power supply path and the sub-power supply path, and the load unit, and performs switching so as to connect one of the main power supply path and the sub-power supply path to the load unit and to disconnect the other from the load unit, according to switching of the power supply selector switch.

Abstract: An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.

Abstract: A power supply device includes a main power supply, a sub-power supply, a main power supply path, a sub-power supply path, a power supply selector switch, and a load selector switch group. The main power supply path is connected to the main power supply. The sub-power supply path is different from the main power supply path and is connected to the sub-power supply. The load selector switch group is disposed between the main power supply path and the sub-power supply path, and the load unit, and performs switching so as to connect one of the main power supply path and the sub-power supply path to the load unit and to disconnect the other from the load unit, according to switching of the power supply selector switch.

Abstract: An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.

Abstract: A CR oscillator has a first logic inversion unit including odd-number stages of logic inversion elements connected in series, a second logic inversion unit including odd-number stages of logic inversion elements connected in series, the second logic inversion unit being connected to a latter stage of the first logic inversion unit, and two or more resistors and a capacitor connected in series between an output node of the first logic inversion unit and an output node of the second logic inversion unit. An electric potential in accordance with an electric potential of an intermediate node between the two or more resistors is supplied to an input node of the first logic inversion unit.

Abstract: A CR oscillator has a first logic inversion unit including odd-number stages of logic inversion elements connected in series, a second logic inversion unit including odd-number stages of logic inversion elements connected in series, the second logic inversion unit being connected to a latter stage of the first logic inversion unit, and two or more resistors and a capacitor connected in series between an output node of the first logic inversion unit and an output node of the second logic inversion unit. An electric potential in accordance with an electric potential of an intermediate node between the two or more resistors is supplied to an input node of the first logic inversion unit.

Abstract: A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. A first diode has a first anode connected to one of the first positive or the first negative terminal. A second diode has a second anode connected to the other of the first negative and first positive terminal. A predetermined reference voltage is applied to the second positive terminal. And a voltage corresponding to the output voltage of the differential amplifier is fed back to the second negative terminal.

Abstract: According to one embodiment, a skew correcting device includes a skew calculation circuit and a sampling timing correction circuit. The skew calculation circuit calculates a skew between data and a strobe signal based on sampling values obtained by sampling, at a cycle one half of or shorter than one half of a cycle of the strobe signal, the data and the strobe signal respectively based on a same clock. The sampling timing correction circuit corrects the sampling timing of the data based on the skew calculated by the skew calculation circuit.

Abstract: A communication device includes a timing generation circuit generates timing signals at several timing points within one period of a first clock signal. A clock sampling circuit receives the first clock signal and detects a logic level of the first clock signal at each of the timing points. A control circuit calculates a difference between the number of times a first or a second logic level is detected for the first clock signal and outputs a control signal indicating whether a duty ratio of the first clock signal is to be adjusted. A correction circuit that changes at a duty ratio of a second clock signal transmitted to the transmitting device, the duty ratio being set in accordance with the control signal. The duty ratio of the first clock signal is then adjusted by the transmitting device according to the duty ratio of the second clock signal.

Abstract: A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. A first diode has a first anode connected to one of the first positive or the first negative terminal. A second diode has a second anode connected to the other of the first negative and first positive terminal. A predetermined reference voltage is applied to the second positive terminal. And a voltage corresponding to the output voltage of the differential amplifier is fed back to the second negative terminal.

Abstract: A communication device includes a timing generation circuit generates timing signals at several timing points within one period of a first clock signal. A clock sampling circuit receives the first clock signal and detects a logic level of the first clock signal at each of the timing points. A control circuit calculates a difference between the number of times a first or a second logic level is detected for the first clock signal and outputs a control signal indicating whether a duty ratio of the first clock signal is to be adjusted. A correction circuit that changes at a duty ratio of a second clock signal transmitted to the transmitting device, the duty ratio being set in accordance with the control signal. The duty ratio of the first clock signal is then adjusted by the transmitting device according to the duty ratio of the second clock signal.

Abstract: According to one embodiment, a skew correcting device includes a skew calculation circuit and a sampling timing correction circuit. The skew calculation circuit calculates a skew between data and a strobe signal based on sampling values obtained by sampling, at a cycle one half of or shorter than one half of a cycle of the strobe signal, the data and the strobe signal respectively based on a same clock. The sampling timing correction circuit corrects the sampling timing of the data based on the skew calculated by the skew calculation circuit.

Abstract: A load controller includes: an input circuit which detects that a drive instruction signal is less or equal to a first input threshold value; a constant current source activated in accordance with a detection by the input circuit; a PWM signal generating unit that is activated by the constant current source and generates a PWM signal; a comparator that is activated by the constant current source and compares the drive instruction signal with a second input threshold value set to be lower than the first input threshold value; a logic calculation unit that carries out a logic calculation of the PWM signal with a compared result of the comparator; a drive control unit that operates in accordance with an output from the logic calculation unit to generate a PWM drive control signal; and a load driving element that is driven by the PWM drive control signal to control a load.

Abstract: A control apparatus for controlling a fuel pump includes: an electronic switch provided in a circuit for connecting a power supply to a motor for driving the fuel pump; a current detector which detects a current which flows through the motor; and a controller which controls the electronic switch in a first PWM mode of a first frequency and a first duty ratio in a normal operation; and change a PWM mode to control the electronic switch in a second PWM mode of a second frequency lower than the first frequency and a second duty ratio lower than the first duty ratio when the current flowing through the motor exceeds a threshold current value in the normal operation.

Abstract: A load controller includes: a first input circuit which detects that a drive instruction signal by an operation of a drive instructing unit is less or equal to a first input threshold value; a first constant current source activated in accordance with the detection; a PWM signal supply unit that is activated by the first constant current source and supplies a PWM signal having a prescribed frequency and a duty ratio; a constant control signal supply unit that supplies a constant control signal during failure of the first input circuit or the first constant current source; a drive control unit that generates a PWM drive control signal in accordance with the PWM signal and generates a constant drive control signal in accordance with the constant control signal; and a load driving element that is controlled by the PWM drive or constant drive control signal to drive a load.

Abstract: A load control unit for controlling the supply of an electric power to a load from battery in accordance with a pulse-width modulation control includes: a reference voltage generating unit; a first charging/discharging unit; a second charging/discharging unit connected in series to the first charging/discharging unit to charge and discharge in reverse to those of the first charging/discharging unit; a first comparing unit that compares the voltage of the first charging/discharging unit with the reference voltage and switches between the charge and discharge of the first charging/discharging unit to generate a triangle wave; and a second comparing unit that compares a divided voltage by dividing the voltage of the battery with the voltage of the triangle wave generated by the first comparing unit to generate a PWM pulse. The ratio of capacities between the first and second charging/discharging units approximates to the ratio of resistances for obtaining the divided voltage.

Abstract: In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than ?8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than ?8° and not more than +8° off the silicon crystal direction.

Abstract: A control device for controlling a recovery from a locking of a motor includes: a switching unit which supplies a motor current from a current supplying unit to the motor; and a driving control unit which supplies a PWM control signal to the switching unit to control a driving of the switching unit. The driving control unit supplies the PWM control signal with a low duty ratio lower than a regular duty ratio to the switching unit when the locking of the motor is detected depending on a variation in temperature of the switching unit. The driving control unit supplies the PWM control signal with the regular duty ratio to the switching unit when a cancel of the locking of the motor is detected depending on a variation in inter-terminal voltage of the motor.