Abstract: Disclosed is a clock distributing apparatus for distributing clock signals with a desired phase to each of devices provided between a clock generating section (10) for generating clock signals and a plurality of devices (30) for receiving the clock signals. A delay generating section (21) generates a plurality of delay clock signals by imparting a plurality of delay quantities to the clock signals from the clock generating section. A clock distributing section (22) has a plurality of input terminals corresponding to the plurality of delay clock signals and a plurality of output terminals corresponding to the respective devices. The clock distributing section (22) distributes desired delay clock signals to one or more output terminals by selecting the input terminals corresponding to the desired delay clock signals.

Abstract: A write address counter for designating a write address of a memory counts up a control counter with an address change. A read address counter for designating a read address of the memory counts down the control counter with the address change. Inputted to an error detecting circuit are a write address counter value, a read address counter value and a control count value. There is detected whether a relationship such as Write Address Count Value-Read Address Count Value=Control Count Value is established or not. If not established, this implies an error, and a reset circuit resets each counter.

Abstract: A packet section (21) generates each packet data by adding a packet header to each of a plurality of random patterns. A highway demultiplexing section (22) demultiplexes the generated packet data to a plurality of input highways. A packet multiplexing section (32) multiplexes the packet data to one highway, the packet data being supplied from the plurality of output highways. A depacket section (31) fetches each random pattern out of the packet data multiplexed by the packet multiplexing section. An error detector (7) detects an error in the random pattern fetched by the depacket section. A test for an under-test device is thus conducted.