Abstract: A hierarchical memory control system including N central processing units each processing unit having a store-in type buffer storage unit; a main storage unit commonly used by the N central processing units; and a global buffer storage unit of a store-in type connected between the central processing units and the main storage unit. The global buffer storage unit is used for storing a data block transferred from the main storage unit, each entry of the global buffer storage unit being larger than each entry of the buffer storage unit, and the data block in each entry of the global buffer storage unit being divided into M divided blocks. In addition, the invention includes a tag unit for managing the entries of the global buffer storage unit, including tags respectively corresponding to the entries of the global buffer storage unit, each tag including managing data for managing the data block.

Abstract: A buffer-storage control system used in a pipeline data processor includes a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage having tag portion and a data portion, each portion being composed of a plurality of partitions. In the buffer-storage control system, the tag portion and the data portion can be independently accessed and the data portion is so constituted for every partition that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every partition, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same partition.

Abstract: An address translation control system comprising an address translation buffer having a plurality of entries each including at least a valid flag, a logical address field, and a physical address field, a memory array having copies of at least the valid flag and the physical address field, and a purge register for storing information showing a portion of the contents of the address translation buffer to partially purge the address translation buffer. When coincidence between the physical address of the address translation buffer and the contents of the purge register does not occur, ordinary access processing is carried out, and when entry of the memory array is accessed in turn and coincidence between the physical address in the memory array and the contents of the purge register occurs, purge is performed by clearing the valid flags of the corresponding entries of the address translation buffer and the memory array.

Abstract: A buffer storage system for a pipeline processor, set up with at least an operand access buffer storage and an instruction fetch buffer storage. The buffer storages cooperate with store address registers and store data registers, to assume a store-through method between the buffer storages and a main storage. A feedback means is mounted between the buffer registers and the store address/data registers. This feedback means is activated during an operand store operation to apply an operand store address and an operand store data, from the store address and store data registers, to the instruction fetch buffer register for effecting coincidence in data among the storages.

Abstract: A computer virtual memory system having a translation lookaside buffer (TLB) in which the result of a dynamic address translation system is stored when in a normal mode or when a non-privileged instruction is executed, but the result is not stored when in a privileged mode or when a privileged instruction is executed, such as a storage key operation. The storage does not occur even though the effective address of the privileged instruction is translated into a physical address.