Patents by Inventor Hiroshi Fukuta

Hiroshi Fukuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8610967
    Abstract: According to one embodiment, illumination apparatus including, first light source module which includes light-emitting module that emits light, light-emitting module having line shape, and first reflection member which includes first reflection surface that reflects light emitted from light-emitting module of first light source module for predetermined range, wherein first reflection surface has cross section that has zigzag line shape including plurality of line segments running along standard oval, which has major axis that forms predetermined angle with direction perpendicular to predetermined range, in direction perpendicular to longitudinal direction of light-emitting module of first light source module.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Ikari, Hiroshi Fukuta, Takeshi Morino, Yoshinori Honguh, Masataka Shiratsuchi
  • Publication number: 20120218611
    Abstract: According to one embodiment, illumination apparatus including, first light source module which includes light-emitting module that emits light, light-emitting module having line shape, and first reflection member which includes first reflection surface that reflects light emitted from light-emitting module of first light source module for predetermined range, wherein first reflection surface has cross section that has zigzag line shape including plurality of line segments running along standard oval, which has major axis that forms predetermined angle with direction perpendicular to predetermined range, in direction perpendicular to longitudinal direction of light-emitting module of first light source module.
    Type: Application
    Filed: May 7, 2012
    Publication date: August 30, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Ikari, Hiroshi Fukuta, Takeshi Morino, Yoshinori Honguh, Masataka Shiratsuchi
  • Patent number: 6539342
    Abstract: In this invention, the detection result indicating physical characteristics obtained from sensor sections and associated with a to-be-detected object for which it is determined that determination of detection thereof by a high-speed detecting process is difficult to make is stored in a data storage unit. Then, in a precise examination processing section, the detecting process is effected on the non-real time basis for a to-be-detected object for which it is determined that the precise examination is necessary by the high-speed detecting process by use of data stored in the data storage unit and the to-be-detected object is distributed into a storage box corresponding to a category of the to-be-detected object as the detection result from the precise examination processing section.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: March 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Matsumoto, Satoshi Watanabe, Hiroshi Fukuta, Masato Suda, Yoshikazu Tagami, Kei Takizawa, Shinya Watanabe
  • Patent number: 6507876
    Abstract: A plurality of sensor portions detect a variety of physical characteristics of objects to be detected, which are being conveyed on a conveyance passage to asynchronously transmit electric signals indicating results of detection to a processing unit. The processing unit causes an A/D converter to A/D-convert the electric signals transmitted from the sensor portions. A mixer adds, to data, an identifier indicating the sensor portion from which data has been transmitted to sequentially output data for each of the sensor portions. A detection-result processing means receives data output from the mixer to identify the sensor portion from which data has been transmitted in accordance with the identifier contained in received data so as to perform a process for detecting the variety of the physical characteristics. The structure and circuit structure of the transmission passage in the detecting apparatus can be simplified.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: January 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Fukuta
  • Publication number: 20020008081
    Abstract: Disclosed is a process for the surface treatment of an aluminum support for printing plate which comprises a step of brush-graining with an abrasive brush and an abrasive slurry, characterized in that as the abrasive there is used aluminum hydroxide, the aluminum hydroxide which has been used in graining is dissolved in a sodium aluminate solution and the sodium aluminate solution having a raised supersaturation degree, the aluminum hydroxide which has been left undissolved and seed crystal aluminum hydroxide undergo hydrolysis reaction to produce crystalline aluminum hydroxide which is then purified and recovered.
    Type: Application
    Filed: August 18, 1998
    Publication date: January 24, 2002
    Inventors: HIROSHI FUKUTA, HIDEKI MIWA
  • Publication number: 20010012987
    Abstract: In this invention, the detection result indicating physical characteristics obtained from sensor sections and associated with a to-be-detected object for which it is determined that determination of detection thereof by a high-speed detecting process is difficult to make is stored in a data storage unit. Then, in a precise examination processing section, the detecting process is effected on the non-real time basis for a to-be-detected object for which it is determined that the precise examination is necessary by the high-speed detecting process by use of data stored in the data storage unit and the to-be-detected object is distributed into a storage box corresponding to a category of the to-be-detected object as the detection result from the precise examination processing section.
    Type: Application
    Filed: December 1, 2000
    Publication date: August 9, 2001
    Inventors: Yuji Matsumoto, Satoshi Watanabe, Hiroshi Fukuta, Masato Suda, Yoshikazu Tagami, Kei Takizawa, Shinya Watanabe
  • Patent number: 5985165
    Abstract: The present invention allows the reproduction of a crystalline aluminum hydroxide having a high particle strength and a high purity which can find wide application such as abrasive from a supersaturated sodium aluminate solution which is being recycled in the production of aluminum hydroxide or lithographic printing plate. In a process for the purification of aluminum hydroxide which comprises the hydrolysis reaction of a supersaturated solution of sodium aluminate to crystallize aluminum hydroxide, the improvement which comprises the steps of keeping the temperature of a suspension formed by mixing a mother liquor having a total caustic soda concentration of from 50 to 700 g/l and an aluminum concentration or from 0 to 300 g/l with crystalline aluminum hydroxide at a range of from 10.degree. C. to 200.degree. C. for at least 1 to 48 hours, mixing the suspension with the supersaturated solution of sodium aluminate, and then causing the crystallization reaction at the crystallization reaction temperature.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: November 16, 1999
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hiroshi Fukuta, Tsutomu Kakei, Tadabumi Tomita, Hideki Miwa
  • Patent number: 5275691
    Abstract: A method and apparatus for treating a surface of an aluminum substrate for a printing plate includes treating the substrate surface with a treatment liquid being circulated, separating and discharging aluminum ions from a portion of the treatment liquid, recovering a sodium hydroxide solution from the treatment liquid, mixing the recovered sodium hydroxide solution with the treatment liquid being circulated, and maintaining a predetermined concentration of aluminum ions in the treatment liquid to be used. A portion of the treatment liquid containing sodium aluminate solution is mixed with aluminum slag containing an amorphous aluminum hydroxide produced at the time of neutralization of a waste acid and a waste alkali produced during surface treatment to thereby supersaturate the sodium aluminate solution, crystallize the aluminum hydroxide, and recover the sodium hydroxide solution to be returned to a liquid control tank to maintain a predetermined concentration of aluminum ions in the treatment liquid.
    Type: Grant
    Filed: February 12, 1992
    Date of Patent: January 4, 1994
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hiroshi Fukuta, Akio Uesugi
  • Patent number: 5267198
    Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: November 30, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta, Kunio Uchiyama, Hirokazu Aoki, Osamu Nishii
  • Patent number: 5202969
    Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: April 13, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering
    Inventors: Katsuyuki Sato, Tadahiko Nishimukai, Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi, Hiroshi Fukuta, Takashi Kikuchi, Yasuhiko Saigou
  • Patent number: 5193075
    Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: March 9, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta, Kunio Uchiyama, Hirokazu Aoki, Osamu Nishii
  • Patent number: 5146573
    Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
    Type: Grant
    Filed: October 25, 1989
    Date of Patent: September 8, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Katsuyuki Sato, Tadahiko Nishimukai, Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi, Hiroshi Fukuta, Takashi Kikuchi, Yasuhiko Saigou
  • Patent number: 5140681
    Abstract: A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.
    Type: Grant
    Filed: May 23, 1989
    Date of Patent: August 18, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Hiroshi Fukuta, Yasuhiko Saigou
  • Patent number: 5129074
    Abstract: A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an internal memory in which data strings are stored. The table contains a plurality of records each including a unit of data, a first index data representative of the number of units of data of a data string which the unit of data constitutes and a second index data unique to each individual data string. The processor elements access in parallel their associated tables under control of the control unit for data storage and data retrieval. The first and index data are generated by the controller for the purpose of data storage.
    Type: Grant
    Filed: September 20, 1989
    Date of Patent: July 7, 1992
    Assignee: Hitachi VLSI Engineering Corporation
    Inventors: Takashi Kikuchi, Hiroshi Fukuta, Nobuo Saito, Oichi Atoda
  • Patent number: 4725742
    Abstract: A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled `on` and `off` by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled `one` and `off` by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled `on` and `off` by the same input signal.
    Type: Grant
    Filed: May 22, 1986
    Date of Patent: February 16, 1988
    Assignees: Hitachi, Ltd., Hitachi VLSI Eng.
    Inventors: Hiroshi Tachimori, Hiroshi Fukuta, Takeshi Fukazawa, Takao Ohkubo, Osamu Takahashi
  • Patent number: 4300213
    Abstract: Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.
    Type: Grant
    Filed: October 31, 1979
    Date of Patent: November 10, 1981
    Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.
    Inventors: Nobuyoshi Tanimura, Hiroshi Fukuta, Kotaro Nishimura, Tokumasa Yasui