Abstract: In a microcomputer including a program memory (1) and a CPU (2) operable in one of high-speed and low-speed modes in which the CPU carries out high-speed and low-speed operations when supplied with high-speed and low-speed clock signals (CKH and CKL), respectively, the program memory includes high-speed and low-speed operation memories (11 and 12) for memorizing high-speed and low-speed mode programs which are read by first and second predetermined address ranges of a program address of a program counter (21) of the CPU and which make the CPU carry out the high-speed and the low-speed operations, respectively. A memory controller (3) produces, when detects the second predetermined address range of the program address, a high-speed operation stop signal for stopping operation of the high-speed operation memory. A clock supplying circuit (4) supplies the CPU with one of the high-speed and the low-speed clock signals that corresponds to one of the high-speed and the low-speed modes.

Abstract: A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder.

Abstract: A user board has an on-board microcomputer including a flash memory and an on-board writing program memory, a user circuit, a reset circuit, a first OR gate, and a second OR gate. A detected signal for resetting the user circuit in an on-board writing mode is supplied from an on-board writing host through the second OR gate to prevent the user circuit from affecting a writing control signal and data to be written into the flash memory.

Abstract: In a data write apparatus to a flash electrically erasable programmable read only memory (EEPROM) built in a microcomputer which is mounted on a circuit board, a write control section first initializes the flash EEPROM to allow data to be written in the flash EEPROM, and supplies a signal indicative of the data for the flash EEPROM. A level converting section convertes a level of the data signal such that the data signal level matches to an actual operation voltage level of the flash EEPROM and supplies the converted data signal to the flash EEPROM such that the data is written in the flash EEPROM.

Abstract: A memory device has memory cells each of which is addressed according to a timing signal, current sense amplifiers each of which determines whether a current flows in the addressed memory cell or not and reads-out the data stored in such memory cell, a circuit which generates a control signal to become active at a timing when the memory cell Is addressed and to become inactive after the read-out of the stored data is completed by the current sense amplifier, and a circuit which cuts-off based on the control signal a current path of a steady-state current flowing in the current sense amplifier. It is possible to substantially reduce power consumption without sacrificing the capability of the read-out the stored data at a high speed.

Abstract: A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.

Abstract: A low frequency oscillator circuit to be integrated in a microcomputer for a low consumption power operation with an improved noise resisting performance. The oscillator circuit includes a high frequency clock generator circuit, a shift register for shifting a low frequency signal by the clock, logical AND and OR circuits each receiving the low frequency signal and the output of the shift register, and a flip-flop circuit to be set and reset by the outputs of the logical AND and OR circuits.

Abstract: A control circuit for a time division multielement display in which a display information generator provides display information to all elements of the display in common, a digital signal generator enables each of the elements in sequence, an active period control circuit controls the enabling signal of the signal generator, and an active period set circuit sets the length of time the control circuit causes an element to be enabled, whereby erroneous displays due to slow transitions are eliminated by shortening the enabled period.