Patents by Inventor Hiroshi Iimura

Hiroshi Iimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6498307
    Abstract: A ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package e.g. when a printed circuit board having the BGA package mounted thereon is carelessly dropped during the manufacturing work, at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package. Thus, the footprints formed on a mounting portion of the BGA package and those formed on the printed circuit board can be prevented from breaking away or being cracked.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: December 24, 2002
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Ichihara, Seiji Kogure, Hiroshi Iimura, Fumio Arase
  • Publication number: 20010030057
    Abstract: There is provided a ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package e.g. when a printed circuit board having the BGA package mounted thereon is carelessly dropped during the manufacturing work, at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package.
    Type: Application
    Filed: July 29, 1998
    Publication date: October 18, 2001
    Applicant: FUJITSU LIMITED
    Inventors: YASUHIRO ICHIHARA, SEIJI KOGURE, HIROSHI IIMURA, FUMIO ARASE
  • Patent number: 5783865
    Abstract: A wiring substrate has a semiconductor device mounted thereonto, the semiconductor device having ball-shaped externally connecting parts. The wiring substrate includes through holes at positions corresponding to the ball-shaped externally connecting parts and electric conductors provided inside and around the through holes. Land portions of the electric conductors, at which the electric conductors are engaged with the externally connecting parts, includes sectional tapering portions, respectively. Further, the through holes have sectional tapering portions at edge portions in proximity to the land portions, respectively. The ball-shaped externally connecting parts of the semiconductor device are engaged with the land portions provided around the through holes of the wiring substrate and having the sectional tapering portions, respectively.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: July 21, 1998
    Assignee: Fujitsu Limited
    Inventors: Yutaka Higashiguchi, Mitsuo Inagaki, Makoto Totani, Yasuhiro Teshima, Hiroshi Iimura
  • Patent number: 5760469
    Abstract: A semiconductor device includes a package having opposing surfaces, a first terminal for an outer connection supported by said package and electronic components supported by said package, and the opposing surfaces of the package having slits so that a shape of the package can be changed in a mounted state. Therefore, stress applied to soldered junctions of the first and second terminals is decreased.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Yutaka Higashiguchi, Mitsuo Inagaki, Toshio Kumai, Ryoichi Ochiai, Yasuhiro Teshima, Mamoru Niishiro, Yasushi Kobayashi, Hideaki Tamura, Hiroshi Iimura, Seishi Chiba, Yukio Sekiya, Shuzo Igarashi, Yasuhiro Ichihara