Patents by Inventor Hiroshi Ishida

Hiroshi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10060654
    Abstract: Heat pump type heating apparatus capable of performing a continuous dual-stage operation without stopping a high stage side compressor even when a return temperature of a heating medium reaches a prescribed high temperature and, thereby, improving a sense of being insufficiently warmed due to stoppage of the high stage side compressor or a sense of being insufficiently warmed due to execution of frequent defrosting operations. The heat pump type heating apparatus includes an internal heat exchanger (a second internal heat exchanger) that performs heat exchange between a low-temperature refrigerant on a low-pressure side of a low stage side refrigeration circuit and a high-temperature refrigerant on a high-pressure side of a high stage side refrigerant circuit, a bypass pipe bypassing the internal heat exchanger, and flow path control means that controls a refrigerant flow to each of the internal heat exchanger and the bypass pipe.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: August 28, 2018
    Assignee: SANDEN HOLDINGS CORPORATION
    Inventors: Yasunori Takayama, Hiroshi Ishida, Masato Sakai, Yoichi Negishi
  • Patent number: 10032122
    Abstract: A computer stores connection information with respect to data items that are management targets. The connection information identifies connection sources and connection destinations. The computer executes a process including performing analysis based on the connection information with respect to first and second data, which are specified as output targets of information indicating connections; outputting first connection information as information indicating a connection between first and second data, when one or a plurality of data items that are connection destinations are traced from the first data set as a connection source, and the second data is reached as a connection destination; and outputting second connection information as information indicating a connection between third and fourth data, when one or a plurality of data items that are connection destinations are traced from the third data set as a connection source, and the fourth data is reached as a connection destination.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 24, 2018
    Assignees: FUJITSU LIMITED, HONDA MOTOR CO., LTD.
    Inventors: Naoki Hashiguchi, Kou Kawanobe, Yasuo Kurosaki, Hiroshi Ishida
  • Publication number: 20180191337
    Abstract: An insulating gate semiconductor device includes an insulating gate semiconductor element, an insulating circuit board, and a main-current path member. A main-current of the insulating gate semiconductor element flows toward a first external terminal in the main-current path member; and a gate-current path member, being patterned so as to have a linearly extending portion arranged in parallel to a linearly extending portion of the main-current path member in a planar pattern on the insulating circuit board, being provided to connect between a second external terminal and a gate electrode of the insulating gate semiconductor element. A current which is induced in the gate-current path member by mutual induction caused by a change in magnetic field implemented by the main-current is used for increasing the gate-current in a turn-on period of the insulating gate semiconductor element.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shinichi Masuda, Shinichi Yoshiwatari, Kenichi Yoshida, Hiroshi Ishida
  • Patent number: 9804049
    Abstract: In a pressure detection device which is provided in an intake pressure measurement apparatus, a detection space surrounded by an outer wall portion is formed in a housing, and an inner wall portion is formed integrally in the detection space such that both end portions are connected to the outer wall portion. The inner wall portion has a cylindrical shape, and a sensor storage portion is formed between the inner wall portion and the outer wall portion. In the sensor storage portion, a pressure sensor is disposed in a region with the least influence of thermal stress at a position closer to the inner wall portion than the outer wall portion.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 31, 2017
    Assignee: ALPS ELECTRIC CO., LTD.
    Inventors: Hisanobu Okawa, Yasuhiro Suda, Hiroshi Ishida, Hideki Kamimura
  • Patent number: 9771351
    Abstract: A Wnt signaling inhibitor which comprises, as an active ingredient, a fused-ring heterocyclic compound represented by the following formula (IA) or a pharmaceutically acceptable salt thereof, and the like are provided: (wherein, n1A represents 0 or 1; n2A and n3A may be the same or different, and each represents 1 or 2; ROA represents optionally substituted aryl or the like; R2A represents a hydrogen atom or the like; R3A represents an optionally substituted aromatic heterocyclic group or the like; X1A, X2A, X3A and X4A each represent CH or the like; Y1A represents CH2 or the like; Y2A represents N or the like; and LA represents CH2 or the like).
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 26, 2017
    Assignee: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: Hiroshi Ishida, Keiichi Motosawa, Yusuke Miura, Ryuichiro Nakai, Ryoko Okada, Yuichi Takahashi
  • Publication number: 20170227260
    Abstract: Heat pump type heating apparatus capable of performing a continuous dual-stage operation without stopping a high stage side compressor even when a return temperature of a heating medium reaches a prescribed high temperature and, thereby, improving a sense of being insufficiently warmed due to stoppage of the high stage side compressor or a sense of being insufficiently warmed due to execution of frequent defrosting operations. The heat pump type heating apparatus includes an internal heat exchanger (a second internal heat exchanger) that performs heat exchange between a low-temperature refrigerant on a low-pressure side of a low stage side refrigeration circuit and a high-temperature refrigerant on a high-pressure side of a high stage side refrigerant circuit, a bypass pipe bypassing the internal heat exchanger, and flow path control means that controls a refrigerant flow to each of the internal heat exchanger and the bypass pipe.
    Type: Application
    Filed: July 2, 2015
    Publication date: August 10, 2017
    Inventors: Yasunori TAKAYAMA, Hiroshi ISHIDA, Yuto SAKAI, Yoichi NEGISHI
  • Patent number: 9663741
    Abstract: An object of this invention is to provide a lubricating base oil that has a small rate of change in viscosity (a high viscosity index) over a wide temperature range, low viscosity at low temperatures, and good low-temperature fluidity and evaporation resistance, and that allows reduced decomposition thereof. To achieve the object, methylpentanediol diesters obtained by using specific aliphatic monocarboxylic acids are used as a lubricating base oil.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 30, 2017
    Assignee: NEW JAPAN CHEMICAL CO., LTD.
    Inventors: Shinya Tsujimoto, Yasuyuki Kawahara, Hiroshi Ishida
  • Publication number: 20160309094
    Abstract: A mobile terminal apparatus includes a geometrical arrangement detecting section (111) detecting groups of edge pixels arranged in a shape of a line segment in an image captured by an image-capturing apparatus; and a display processing section (112) causes a contour line representative of a contour of a rectangular captured object to be displayed on the captured image displayed on a display section so that the contour line is superimposed on the groups of edge pixels detected by the geometrical arrangement detecting section (111).
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventor: Hiroshi ISHIDA
  • Patent number: 9412755
    Abstract: In a manufacturing method for a semiconductor device provided with a MONOS-type FET for a non-volatile memory and high-voltage and low-voltage MOSFETs, a groove having a predetermined depth is formed in a region in which the high-voltage MOSFET on a semiconductor substrate is formed, and an oxide film serving as a gate insulating film of the high-voltage MOSFET is formed within the formed groove by thermal oxidation. Thereafter, a gate electrode film of the low-voltage MOSFET is formed on the entire surface of the semiconductor substrate. Thereafter, a region for the MONOS-type FET is opened, the semiconductor surface of the semiconductor substrate is exposed, and a first potential barrier film, a charge storage film, and a second potential barrier film are sequentially deposited, to thereby form a charge storage three-layer film. Agate electrode film of the MONOS-type FET is formed on the formed charge storage three-layer film.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: August 9, 2016
    Assignee: Synaptics Display Devices GK
    Inventors: Hiroshi Ishida, Kazuhiko Sato
  • Patent number: 9412015
    Abstract: A mobile terminal apparatus includes a geometrical arrangement detecting section (111) detecting groups of edge pixels arranged in a shape of a line segment in an image captured by an image-capturing apparatus; and a display processing section (112) causes a contour line representative of a contour of a rectangular captured object to be displayed on the captured image displayed on a display section so that the contour line is superimposed on the groups of edge pixels detected by the geometrical arrangement detecting section (111).
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: August 9, 2016
    Assignee: Sharp Kabushiki Kaishi
    Inventor: Hiroshi Ishida
  • Patent number: 9412599
    Abstract: A gate oxide film is formed in a region having a MOSFET on a semiconductor substrate formed therein, and a first polysilicon film serving as a gate electrode of the MOSFET is further formed. Thereafter, a charge storage three-layer film is formed by opening a region having a MONOS type FET formed therein, exposing a semiconductor surface of the semiconductor substrate, and sequentially depositing a first potential barrier film, a charge storage film, and a second potential barrier film. In this case, before the charge storage three-layer film is formed, an anti-oxidation film is formed on the first polysilicon film.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: August 9, 2016
    Assignee: Synaptics Display Devices GK
    Inventors: Hiroshi Ishida, Kazuhiko Sato
  • Publication number: 20160168125
    Abstract: A Wnt signaling inhibitor which comprises, as an active ingredient, a fused-ring heterocyclic compound represented by the following formula (IA) or a pharmaceutically acceptable salt thereof, and the like are provided: (wherein, n1A represents 0 or 1; n2A and n3A may be the same or different, and each represents 1 or 2; ROA represents optionally substituted aryl or the like; R2A represents a hydrogen atom or the like; R3A represents an optionally substituted aromatic heterocyclic group or the like; X1A, X2A, X3A and X4A each represent CH or the like; Y1A represents CH2 or the like; Y2A represents N or the like; and LA represents CH2 or the like).
    Type: Application
    Filed: July 29, 2014
    Publication date: June 16, 2016
    Applicant: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: Hiroshi ISHIDA, Keiichi MOTOSAWA, Yusuke MIURA, Ryuichiro NAKAI, Ryoko OKADA, Yuichi TAKAHASHI
  • Patent number: 9244298
    Abstract: A liquid crystal display device includes a liquid crystal (LC) panel; front and rear frames sandwiching therebetween the LC panel; a latch structure engaging together the LC panel and one of the front and rear frames. The latch structure includes a convex portion formed on one of the LC panel and the one of the front and rear panels and a concave portion formed on the other of the LC panel and the one of the front and rear frames to receive therein the convex portion, whereby the latch structure allows and restricts movement of the LC panel with respect to the one of the front and rear frames in a first direction normal to the LC panel and in a second direction parallel to the LC panel, respectively.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 26, 2016
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventor: Hiroshi Ishida
  • Patent number: 9236027
    Abstract: The present invention provides a display system capable of efficiently calibrating image content even when the image is displayed and thereby capable of reducing the time and cost required for calibration, and also provides a computer-readable recording medium. The control device thereof processes an image to be displayed on a display section beforehand so as to be usable for calibration. While the image is actually being displayed on the display section, the control device captures an image displayed on the display section using a capturing device at the timing at which a calibration image is displayed, compares the luminance or color in the calibration image with the luminance or color in the image obtained by capturing the calibration image, and creates correction information for correcting an image signal to be output to the display section on the basis of the result of the comparison.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: January 12, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hiroshi Ishida
  • Patent number: 9214354
    Abstract: In a manufacturing method of sequentially forming a gate electrode film of the MOSFET, forming a gate electrode film of the non-volatile memory FET, patterning the gate electrode of the non-volatile memory FET, and patterning the gate electrode of the MOSFET, in order to form the MOSFET and the non-volatile memory FET on the same semiconductor substrate. The value of the product of S/L and H/L is specified in a case that the line of the gate electrode of the non-volatile memory FET is set to L, the space thereof is set to S, and the height thereof is set to H so that the thickness of a resist film on the gate electrode of the non-volatile memory FET which is formed in advance is set to a thickness which is not lost by etching for forming the gate electrode of the MOSFET.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: December 15, 2015
    Assignee: Synaptics Display Devices GK
    Inventors: Hiroshi Ishida, Kazuhiko Sato
  • Publication number: 20150227552
    Abstract: A non-transitory computer-readable recording medium stores a data management program that causes a computer to execute a process. The computer is configured to store data, which is a development deliverable of a product, in one of folders included in a storage folder group having a hierarchal structure. The process includes referring to a storage unit storing a plurality of items constituting an ISO (International Organization for Standardization) specification defining a development process of the product; outputting one or more items as options among the plurality of items constituting the ISO specification defining the development process of the product, when applying an attribute to the one of the folders included in the storage folder group; and implementing control to store the attribute corresponding to a selected item among the one or more items that have been output in association with the one of the folders.
    Type: Application
    Filed: January 13, 2015
    Publication date: August 13, 2015
    Applicants: FUJITSU LIMITED, HONDA MOTOR CO., LTD.
    Inventors: Naoki Hashiguchi, Masayuki Okishio, Yasuo Kurosaki, Hiroshi Ishida
  • Publication number: 20150229551
    Abstract: A computer stores connection information with respect to data items that are management targets. The connection information identifies connection sources and connection destinations. The computer executes a process including performing analysis based on the connection information with respect to first and second data, which are specified as output targets of information indicating connections; outputting first connection information as information indicating a connection between first and second data, when one or a plurality of data items that are connection destinations are traced from the first data set as a connection source, and the second data is reached as a connection destination; and outputting second connection information as information indicating a connection between third and fourth data, when one or a plurality of data items that are connection destinations are traced from the second data set as a connection source, and the fourth data is reached as a connection destination.
    Type: Application
    Filed: January 13, 2015
    Publication date: August 13, 2015
    Applicants: FUJITSU LIMITED, HONDA MOTOR CO., LTD.
    Inventors: Naoki HASHIGUCHI, Kou KAWANOBE, Yasuo KUROSAKI, Hiroshi ISHIDA
  • Publication number: 20150227532
    Abstract: A computer stores a file in a folder. The computer executes a process including acquiring identification information of files included in a single archive file, when the folder stores the single archive file, the single archive file being generated by integrating the files and performing a compression process, or by integrating the files; outputting the acquired identification information of the files as candidates that may be associated with another folder, file, or an individual data object in another file, which is managed by the computer; and storing association information with respect to one of the files which is specified to be associated with another folder, file, or an individual data object included in another file, the association information being information for associating the one of the files with another folder, or file, or an individual data object included in another file, which is a target of association.
    Type: Application
    Filed: January 13, 2015
    Publication date: August 13, 2015
    Applicants: FUJITSU LIMITED, HONDA MOTOR CO., LTD.
    Inventors: Naoki HASHIGUCHI, Kou KAWANOBE, Hiroshi ISHIDA
  • Publication number: 20150171101
    Abstract: In a manufacturing method for a semiconductor device provided with a MONOS-type FET for a non-volatile memory and high-voltage and low-voltage MOSFETs, a groove having a predetermined depth is formed in a region in which the high-voltage MOSFET on a semiconductor substrate is formed, and an oxide film serving as a gate insulating film of the high-voltage MOSFET is formed within the formed groove by thermal oxidation. Thereafter, a gate electrode film of the low-voltage MOSFET is formed on the entire surface of the semiconductor substrate. Thereafter, a region for the MONOS-type FET is opened, the semiconductor surface of the semiconductor substrate is exposed, and a first potential barrier film, a charge storage film, and a second potential barrier film are sequentially deposited, to thereby form a charge storage three-layer film. Agate electrode film of the MONOS-type FET is formed on the formed charge storage three-layer film.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Inventors: Hiroshi ISHIDA, Kazuhiko SATO
  • Publication number: 20150171103
    Abstract: In a manufacturing method of sequentially forming a gate electrode film of the MOSFET, forming a gate electrode film of the non-volatile memory FET, patterning the gate electrode of the non-volatile memory FET, and patterning the gate electrode of the MOSFET, in order to form the MOSFET and the non-volatile memory FET on the same semiconductor substrate. The value of the product of S/L and H/L is specified in a case that the line of the gate electrode of the non-volatile memory FET is set to L, the space thereof is set to S, and the height thereof is set to H so that the thickness of a resist film on the gate electrode of the non-volatile memory FET which is formed in advance is set to a thickness which is not lost by etching for forming the gate electrode of the MOSFET.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Inventors: Hiroshi ISHIDA, Kazuhiko SATO