Patents by Inventor Hiroshi Ishioka

Hiroshi Ishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240158676
    Abstract: Provided is a conductive adhesive sheet that has excellent connection stability even containing conductive particles in a small proportion. The inventive conductive adhesive sheet contains a binder component and conductive particles. The conductive particles are distributively arranged. Assume that all the conductive particles are regularly arranged; and that an optional region of the conductive adhesive sheet is viewed in plan view so that a distribution number Np of the distributed conductive particles be 9 to 25, a condition: 1.5X?Y?100X is met, where X represents the average of equivalent circle diameters of the distributed conductive particles; and Y represents the center-to-center distance between adjacent two of the distributed conductive particles, which are regularly arranged in the plan view. The ratio N/Np is 1.0 to 100.0, where N represents the number of the primary particles in the optional region.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Yuusuke HARUNA, Kenji AOKI, Hiroshi TAJIMA, Sougo ISHIOKA
  • Patent number: 8766699
    Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 1, 2014
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Hiroshi Ishioka
  • Patent number: 8760223
    Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: June 24, 2014
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Hiroshi Ishioka
  • Patent number: 8536930
    Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 17, 2013
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Satoshi Hatsukawa, Nobuo Shiga, Kazuhiro Fujikawa, Takashi Ohira, Kazuyuki Wada, Tuya Wuren, Kazushi Sawada, Hiroshi Ishioka
  • Publication number: 20120326774
    Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.
    Type: Application
    Filed: June 27, 2012
    Publication date: December 27, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi HATSUKAWA, Nobuo SHIGA, Kazuhiro FUJIKAWA, Takashi OHIRA, Kazuyuki WADA, Tuya WUREN, Kazuya ISHIOKA, Kazushi SAWADA, Hiroshi Ishioka
  • Publication number: 20120306288
    Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation Toyohashi University Of Technology, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka
  • Publication number: 20120306563
    Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro FUJIKAWA, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka
  • Patent number: 5953286
    Abstract: In a semiconductor memory including a plurality of synchronous DRAMs controlled by one common memory controller, each of the synchronous DRAMs has first and second terminals for receiving a reference clock supplied from the memory controller. A signal line for this reference clock is laid out in such a manner that the signal line is connected from the memory controller firstly to the first terminal of the most remote synchronous DRAM, and then, to respective first terminals of the remaining synchronous DRAMs, in order, towards the nearest synchronous DRAM and further, to the second terminal of the nearest synchronous DRAM, and then, to respective second terminals of the remaining synchronous DRAMs, in order, towards the most remote synchronous DRAM.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: September 14, 1999
    Assignee: NEC Corporation
    Inventors: Yasushi Matsubara, Hiroshi Ishioka
  • Patent number: 5089876
    Abstract: A semiconductor IC device includes a semiconductor pellet, an insulating film, a conductive plate, and a lead frame. A plurality of electrodes and a plurality of active elements are formed on the semiconductor pellet. The insulating film is bonded to a surface of the semiconductor pellet on which the active elements are formed. The conductive plate is arranged on the insulating film. The lead frame includes a plurality of connecting terminals selectively arranged in predetermined regions on the conductive plate through another insulating film, and leads laterally extending from the connecting terminals.
    Type: Grant
    Filed: July 19, 1990
    Date of Patent: February 18, 1992
    Assignee: NEC Corporation
    Inventor: Hiroshi Ishioka
  • Patent number: 4874818
    Abstract: A primer composition usable for steel sheet and plastic sheet in vehicle bodies consists mainly of a polycaprolactone graft polymer obtained by graft-polymerizing a styrene-butadiene-styrene block copolymer or its hydrogenated polymer with a ring-opened polymer of .epsilon.-caprolactone and having a grafting ratio of the ring-opened polymer within a range of 0.5.about.50% by weight.
    Type: Grant
    Filed: July 28, 1987
    Date of Patent: October 17, 1989
    Assignee: Nippon Oil and Fats Co., Ltd.
    Inventors: Shosaku Yamamoto, Kazuo Kakinuma, Hiroshi Ishioka, Fumio Sodeyama, Junji Mayumi, Riichiro Maruta
  • Patent number: 4733285
    Abstract: An MOSIC is provided with an input and/or output protective circuit which includes a first semiconductor region formed in a semiconductor substrate with a PN junction and electrically coupled between an input or output terminal and a transistor to be protected and a second semiconductor region formed so as to surround the first region. The PN junction formed between the second region and the substrate is reverse-biased, whereby the second region absorbs carriers which are undesirably injected from the first region into the substrate in an electrical operation of the IC.
    Type: Grant
    Filed: July 24, 1985
    Date of Patent: March 22, 1988
    Assignee: NEC Corporation
    Inventors: Hiroshi Ishioka, Tohru Tsujide, Makoto Miyazawa