Abstract: The surface of an epitaxial wafer is inspected using an optical scattering method. The intensities of light scattered with a narrow scattering angle and light scattered with a wide scattering angle reflected from laser light scatterers (LLS) on the wafer surface are detected. If the intensifies of narrowly and widely scattered lights are within a prescribed sizing range, it is judged whether the laser light scatterer is a particle or killer defect by deciding into which zone (410, 414, 418, 439) within the sizing range the PLS size based on the narrowly scattered light intensity and the PLS size based, on the widely scattered light intensity fall. If the intensity of the narrowly or widely scattered light exceeds the sizing range (417, 420, 421, 423, 424, 425), or if a plenty of laser light scatterers are continuous or concentrated (422), the laser light scatterers are judged to be killer defects.

Abstract: The surface of an epitaxial wafer is inspected using an optical scattering method. The intensities of light scattered with a narrow scattering angle and light scattered with, a wide scattering angle reflected from laser light scatterers (LLS) on the wafer surface are detected. If the intensifies of narrowly and widely scattered lights are within a prescribed sizing range, it is judged whether the laser light scatterer is a particle or killer defect by deciding into which zone (410, 414, 418, 439) within the sizing range the PLS size based on the narrowly scattered light intensity and the PLS size based, on the widely scattered light intensity fall. If the intensity of the narrowly or widely scattered light exceeds the sizing range (417, 420, 421, 423, 424, 425), or if a plenty of laser light scatterers are continuous or concentrated (422), the laser light scatterers are judged to be killer defects.

Abstract: Multiple epitaxial layers are grown on the front side of a p silicon substrate and no layers are grown on the other side. Among the multiple epitaxial layers the one in contact with the silicon substrate is a first p+ epitaxial layer. Since the epitaxial layer is in contact with the p+ layer, gettering can be efficiently done also in a low-temperature device manufacturing process, thereby improving the manufacturing yield of an epitaxial wafer. Therefore the manufacturing cost of an epitaxial wafer is reduced.