Abstract: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.

Abstract: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.

Abstract: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.

Abstract: A semiconductor device including a pillar formed in a highly reliable manner and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a semiconductor chip including an internal circuit area and an I/O area disposed outside the internal circuit area, a package substrate coupled in a flip-chip manner to the semiconductor chip, and an electrically conductive pillar disposed between the semiconductor chip and the package substrate such that the electrically conductive pillar is located over two or more wirings in an uppermost wiring layer of the semiconductor chip and such that the two or more wirings are coupled together via the electrically conductive pillar.

Abstract: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.

Abstract: Placement is performed by using a library created by enlarging cell frames of at least one type of cells out of a plurality of types of standard cells constituted by using transistors having different characteristics for the respective types of cell. More preferably, the overlap between cells is judged by using unenlarged cell frames as adjacent boundaries for standard cells of the same type, and the overlap between cells is judged by using enlarged cell frames as adjacent boundaries for standard cells of different types. This enables automatic placement in which different types of cells are mixed.

Abstract: Placement is performed by using a library created by enlarging cell frames of at least one type of cells out of a plurality of types of standard cells constituted by using transistors having different characteristics for the respective types of cell. More preferably, the overlap between cells is judged by using unenlarged cell frames as adjacent boundaries for standard cells of the same type, and the overlap between cells is judged by using enlarged cell frames as adjacent boundaries for standard cells of different types. This enables automatic placement in which different types of cells are mixed.