Patents by Inventor Hiroshi Koguchi

Hiroshi Koguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230072579
    Abstract: A metal foil has a cathode surface on which no linear indentations exist when viewed microscopically, a production method for the same, and a processing method for an electrodeposition drum used for the same. A surface of the electrodeposition drum for producing the metal foil is irradiated with a laser to process this surface into a pattern of repeated curved shapes including a plurality of dot-shaped dents or the like. With this, the pattern of repeated curved shapes is formed on the surface of the electrodeposition drum. The electrodeposition drum thus processed is used as a cathode, supply of electricity is provided between the electrodeposition drum and an anode plate that are soaked in an electrolytic solution to electrodeposit metal on the surface of the drum with an electrolytic reaction, and thereafter, the metal is peeled off from the electrodeposition drum, thereby yielding the metal foil.
    Type: Application
    Filed: January 28, 2021
    Publication date: March 9, 2023
    Inventors: Hiroshi KOGUCHI, Yuya SAGIYA, Nobuchika YAGIHASHI
  • Patent number: 7529260
    Abstract: There is provided a packet transmission apparatus, system and method that are implemented in an apparatus generating a packet to send out packet generated toward another device via a network bus, including: generating a first packet having a first header and contents data; inputting a data string of the first packet to a buffer from its head successively; determining whether the network bus is available in case where a predetermined data sending condition is satisfied; reading out contents data that is input to the buffer and that is not yet read out from the buffer, in case where the network bus is available; generating a second header on the basis of a size of the contents data read out and the first header; adding the second header to the contents data read out to generate a second packet; and outputting the generated second packet to the network bus.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Koguchi
  • Patent number: 7400656
    Abstract: There is provided a time stamp correction apparatus for being used in an apparatus which receives a packet including real time data and a time stamp based on network time from a network and reproduces the real time data on the basis of the time stamp, the time stamp correction apparatus including: receiving a first packet including the real time data and a first time stamp; successively generating the network time according to synchronous information input from the network; calculating a difference between time by the first time stamp and the network time; successively generating local time; generating a second time stamp based on the difference and the local time; generating a second packet by adding the second time stamp to the real time data; storing the generated second packet into a buffer unit; and conducting output control on the second packet on the basis of the local time.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Koguchi
  • Patent number: 7319704
    Abstract: A device capable of correcting time stamp value according to an embodiment of the present invention including an original time counter configured to generate and output an original time value, a subtracter configured to receive a network time value from the outside and the original time value from the original time counter, subtract the original time value from the network time value, and output the difference as a cycle-time difference value, and a first adder configured to receive an original time-stamp value generated from the original time value and the cycle-time difference value from the subtracter, add the cycle-time difference value to the original time-stamp value, and output the sum as a time-stamp value.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: January 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Koguchi
  • Patent number: 7249226
    Abstract: A semiconductor system according to an embodiment of the present invention comprises a shared memory; a plurality of processing units each of which designates a memory size and a memory address, and which uses the shared memory; an address allocation unit which allocates memory addresses having the memory size designated by the each processing unit to the processing unit; and an address conversion unit which converts the memory address designated by the each processing unit into one of the memory addresses allocated to the processing unit, the converted memory address being including in the shared memory and being accessed by the processing unit.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Koguchi, Yusuke Ishizawa
  • Publication number: 20050265334
    Abstract: There is provided a time stamp correction apparatus for being used in an apparatus which receives a packet including real time data and a time stamp based on network time from a network and reproduces the real time data on the basis of the time stamp, the time stamp correction apparatus including: receiving a first packet including the real time data and a first time stamp; successively generating the network time according to synchronous information input from the network; calculating a difference between time by the first time stamp and the network time; successively generating local time; generating a second time stamp based on the difference and the local time; generating a second packet by adding the second time stamp to the real time data; stores the generated second packet into a buffer unit; and conducting output control on the second packet on the basis of the local time.
    Type: Application
    Filed: March 25, 2005
    Publication date: December 1, 2005
    Inventor: Hiroshi Koguchi
  • Publication number: 20050243866
    Abstract: There is provided a packet transmission apparatus, system and method that are implemented in an apparatus generating a packet to send out packet generated toward another device via a network bus, including: generating a first packet having a first header and contents data; inputting a data string of the first packet to a buffer from its head successively; determining whether the network bus is available in case where a predetermined data sending condition is satisfied; reading out contents data that is input to the buffer and that is not yet read out from the buffer, in case where the network bus is available; generating a second header on the basis of a size of the contents data read out and the first header; adding the second header to the contents data read out to generate a second packet; and outputting the generated second packet to the network bus.
    Type: Application
    Filed: March 31, 2005
    Publication date: November 3, 2005
    Inventor: Hiroshi Koguchi
  • Publication number: 20050102485
    Abstract: A semiconductor system according to an embodiment of the present invention comprises a shared memory; a plurality of processing units each of which designates a memory size and a memory address, and which uses the shared memory; an address allocation unit which allocates memory addresses having the memory size designated by the each processing unit to the processing unit; and an address conversion unit which converts the memory address designated by the each processing unit into one of the memory addresses allocated to the processing unit, the converted memory address being including in the shared memory and being accessed by the processing unit.
    Type: Application
    Filed: September 1, 2004
    Publication date: May 12, 2005
    Inventors: Hiroshi Koguchi, Yusuke Ishizawa
  • Publication number: 20040136375
    Abstract: A device capable of correcting time stamp value according to an embodiment of the present invention including an original time counter configured to generate and output an original time value, a subtracter configured to receive a network time value from the outside and the original time value from the original time counter, subtract the original time value from the network time value, and output the difference as a cycle-time difference value, and a first adder configured to receive an original time-stamp value generated from the original time value and the cycle-time difference value from the subtracter, add the cycle-time difference value to the original time-stamp value, and output the sum as a time-stamp value.
    Type: Application
    Filed: September 23, 2003
    Publication date: July 15, 2004
    Inventor: Hiroshi Koguchi