Patents by Inventor Hiroshi Kotaki

Hiroshi Kotaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985489
    Abstract: In a sound processing method of operating audio equipment to perform sound processing relating to audio content in accordance with one embodiment, a distributor terminal communicates with the audio equipment and at least one listener terminal, the distributor terminal distributes the audio content from the distributor terminal to the at least one listener terminal, the distributor terminal specifies an operation listener terminal, from among the at least one listener terminal, that is permitted to change a sound processing parameter of the audio equipment, the operation listener terminal accepts the sound processing parameter changed by the operation listener terminal, the operation listener terminal transmits the sound processing parameter changed by the operation listener terminal to the distributor terminal, and the audio equipment performs the sound processing based on the changed sound processing parameter changed by the operation listener terminal.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: May 14, 2024
    Assignee: YAMAHA CORPORATION
    Inventors: Hiroshi Kotaki, Mitsutaka Goto, Mizuyuki Shirai, Akihiro Sonogi, Takahiro Senda, Hitomi Shimizu
  • Patent number: 11694824
    Abstract: The purpose of the present invention is to provide a method for causing sufficient deformation in precursor particles even when a soft high-purity metal is used for an outer layer material in mechanical milling, and manufacturing an MgB2 superconducting wire. A method for manufacturing an MgB2 superconducting wire in which an MgB2 filament is covered by an outer layer material, the method comprising: subjecting magnesium powder and boron powder to a shock that is insufficient for MgB2 to be clearly produced, and producing precursor particles in which boron particles are dispersed inside a magnesium matrix; filling a metal tub with the precursor particles; processing the metal tube filled with precursor particles to form a wire; and heat-treating the wire to synthesize the MgB2; wherein the method is characterized in that a portion of the wire-drawing step includes swaging.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 4, 2023
    Assignee: HITACHI, LTD.
    Inventors: Motomune Kodama, Hideki Tanaka, Takaaki Suzuki, Hiroshi Kotaki
  • Patent number: 11562836
    Abstract: The present invention is intended to increase the critical current density of a wire rod having a shape with good symmetry such as a round wire or a square wire by making use of mechanical milling method. The production method of the present invention for the MgB2 superconducting wire rod comprises a mixing process of preparing a powder by adding a solid organic compound to a magnesium powder and a boron powder and then applying an impact to the powder to prepare a mixture of the powder in which boron particles are dispersed inside magnesium particles, a filling process of filling a metal tube with the mixture, an elongation process of elongating the metal tube filled with the mixture and a heat treatment process of heat-treating the metal tube to synthesize MgB2.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 24, 2023
    Assignee: HITACHI, LTD.
    Inventors: Motomune Kodama, Shigeho Tanigawa, Hiroshi Kotaki, Hideki Tanaka, Kazuya Nishi, Takaaki Suzuki
  • Publication number: 20230010955
    Abstract: In a sound processing method of operating audio equipment to perform sound processing relating to audio content in accordance with one embodiment, a distributor terminal communicates with the audio equipment and at least one listener terminal, the distributor terminal distributes the audio content from the distributor terminal to the at least one listener terminal, the distributor terminal specifies an operation listener terminal, from among the at least one listener terminal, that is permitted to change a sound processing parameter of the audio equipment, the operation listener terminal accepts the sound processing parameter changed by the operation listener terminal, the operation listener terminal transmits the sound processing parameter changed by the operation listener terminal to the distributor terminal, and the audio equipment performs the sound processing based on the changed sound processing parameter changed by the operation listener terminal.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 12, 2023
    Inventors: Hiroshi KOTAKI, Mitsutaka GOTO, Mizuyuki SHIRAI, Akihiro SONOGI, Takahiro SENDA, Hitomi SHIMIZU
  • Publication number: 20200294693
    Abstract: The purpose of the present invention is to provide a method for causing sufficient deformation in precursor particles even when a soft high-purity metal is used for an outer layer material in mechanical milling, and manufacturing an MgB2 superconducting wire. A method for manufacturing an MgB2 superconducting wire in which an MgB2 filament is covered by an outer layer material, the method comprising: subjecting magnesium powder and boron powder to a shock that is insufficient for MgB2 to be clearly produced, and producing precursor particles in which boron particles are dispersed inside a magnesium matrix; filling a metal tub with the precursor particles; processing the metal tube filled with precursor particles to form a wire; and heat-treating the wire to synthesize the MgB2; wherein the method is characterized in that a portion of the wire-drawing step includes swaging.
    Type: Application
    Filed: November 2, 2018
    Publication date: September 17, 2020
    Applicant: Hitachi, Ltd.
    Inventors: Motomune Kodama, Hideki Tanaka, Takaaki Suzuki, Hiroshi Kotaki
  • Publication number: 20200091397
    Abstract: Provided is an MgB2 superconductive thin film wire material allowing for lower costs while maintaining superconductive properties that are equal to or greater than those of the MgB2 superconductive thin film wire material of prior art, and to provide a production method for the superconductive thin film wire material. The MgB2 superconductive thin film wire material according to the present invention is a superconductive wire material comprising an MgB2 thin film formed over an elongated metal base material, characterized in that the MgB2 thin film exhibits a critical temperature of 30 K or higher, and has a microscopic organization wherein MgB2 columnar crystal grains stand densely packed on the surface of the elongated metal base material, and a layer of Mg oxide is formed in such a manner as to surround the MgB2 columnar crystal grains in the grain boundary regions of the MgB2 columnar crystal grains.
    Type: Application
    Filed: March 7, 2018
    Publication date: March 19, 2020
    Applicant: HITACHI, LTD.
    Inventors: Takumu IWANAKA, Hiroshi KOTAKI, Toshiaki KUSUNOKI
  • Publication number: 20200090835
    Abstract: The present invention is intended to increase the critical current density of a wire rod having a shape with good symmetry such as a round wire or a square wire by making use of mechanical milling method. The production method of the present invention for the MgB2 superconducting wire rod comprises a mixing process of preparing a powder by adding a solid organic compound to a magnesium powder and a boron powder and then applying an impact to the powder to prepare a mixture of the powder in which boron particles are dispersed inside magnesium particles, a filling process of filling a metal tube with the mixture, an elongation process of elongating the metal tube filled with the mixture and a heat treatment process of heat-treating the metal tube to synthesize MgB2.
    Type: Application
    Filed: March 10, 2017
    Publication date: March 19, 2020
    Inventors: Motomune KODAMA, Shigeho TANIGAWA, Hiroshi KOTAKI, Hideki TANAKA, Kazuya NISHI, Takaaki SUZUKI
  • Publication number: 20190253797
    Abstract: An operation reception device includes a display to display a current value, a physical operator to receive an operation in a one-way direction, and a controller configured to when the physical operator is not being operated by the user, set as a reference state an operating state corresponding to the current value, and in response to user operation of the physical operator, change the current value of the reference state.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 15, 2019
    Inventors: Shintaro NOGUCHI, Hiroshi KOTAKI
  • Publication number: 20190214851
    Abstract: A power supply device including at least two power transmission coils is provided. The directions of the planes of at least two power transmission coils are different from each other. The frequencies of the at least two power transmission coils are different from each other. Preferably, the at least two power transmission coils include at least three power transmission coils. The directions of the planes of the at least three power transmission coils are different from each other.
    Type: Application
    Filed: May 12, 2017
    Publication date: July 11, 2019
    Inventors: MASATO SASAKI, HIROSHI KOTAKI, HIROSHI KAWAMURA, AKIHIDE SHIBATA, HIROSHI ITOH
  • Publication number: 20190035519
    Abstract: The present invention addresses the problem of providing a wire material capable of ensuring high critical current density, regardless of the cross-sectional shape thereof. This super-conducting wire material is equipped with an MgB2 filament, the number density of cavities having a major axis of 10 ?m or higher in a longitudinal cross-section of the superconducting wire material is in the range of 5-500 mm?2, and the average value of the angle formed between the major axis of the cavities and the axis of the wire material is 60 degrees or more.
    Type: Application
    Filed: January 10, 2017
    Publication date: January 31, 2019
    Applicant: HITACHI, LTD.
    Inventors: Motomune KODAMA, Hideki TANAKA, Hiroshi KOTAKI, Kazuya NISHI, Takaaki SUZUKI
  • Patent number: 8421116
    Abstract: The light emitting device of the invention comprises a first electrode, a second electrode being light transmitting, and a carrier sandwiched between the first electrode and the second electrode and containing light emitters, wherein the first electrode has a plurality of projections or a pn junction formed with a p-type semiconductor and an n-type semiconductor each on a surface being in contact with the carrier.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobutoshi Arai, Masatomi Harada, Takayuki Ogura, Hiroshi Kotaki
  • Patent number: 8139395
    Abstract: There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: March 20, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Kotaki, Yoshiji Ohta, Syuji Wakaiki
  • Publication number: 20100296330
    Abstract: There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 25, 2010
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiroshi KOTAKI, Yoshiji Ohta, Syuji Wakaiki
  • Publication number: 20100140642
    Abstract: The light emitting device of the invention comprises a first electrode, a second electrode being light transmitting, and a carrier sandwiched between the first electrode and the second electrode and containing light emitters, wherein the first electrode has a plurality of projections or a pn junction formed with a p-type semiconductor and an n-type semiconductor each on a surface being in contact with the carrier.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 10, 2010
    Inventors: Nobutoshi ARAI, Masatomi HARADA, Takayuki OGURA, Hiroshi KOTAKI
  • Patent number: 7080604
    Abstract: A lower thread supplying apparatus for a sewing machine has a bobbin accommodating portion 11 for detachably accommodating a lower thread bobbin 12 from an opening part 101c, a tension applying portion 13 for hitching a lower thread, a lower thread cutting knife 14 provided at the end portion of a lower thread passing route with a predetermined length, a cover 15 for covering the opening part 101c, a cover plate 20 for covering around the lower thread bobbin 12, a bending portion 16, a first guide portion 30 for introducing the lower thread to the bending portion and a second guide portion 40 for introducing the lower thread to the lower thread cutting knife. The bobbin accommodating portion, the tension applying portion, the bending portion and the lower thread cutting knife are provided at an inner area of the opening part 101c.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: July 25, 2006
    Assignee: Juki Corporation
    Inventors: Kuniharu Sakuma, Yumiko Kotaki, legal representative, Atsushi Shiraishi, Hiroshi Kotaki, deceased
  • Publication number: 20050211145
    Abstract: A lower thread supplying apparatus for a sewing machine has a bobbin accommodating portion 11 for detachably accommodating a lower thread bobbin 12 from an opening part 101c, a tension applying portion 13 for hitching a lower thread, a lower thread cutting knife 14 provided at the end portion of a lower thread passing route with a predetermined length, a cover 15 for covering the opening part 101c, a cover plate 20 for covering around the lower thread bobbin 12, a bending portion 16, a first guide portion 30 for introducing the lower thread to the bending portion and a second guide portion 40 for introducing the lower thread to the lower thread cutting knife. The bobbin accommodating portion, the tension applying portion, the bending portion and the lower thread cutting knife are provided at an inner area of the opening part 101c.
    Type: Application
    Filed: January 24, 2005
    Publication date: September 29, 2005
    Applicant: JUKI CORPORATION
    Inventors: Kuniharu Sakuma, Hiroshi Kotaki, Atsushi Shiraishi, Yumiko Kotaki
  • Patent number: 5391508
    Abstract: A method of forming semiconductor devices comprising the steps of forming, by restriction in the increased number of steps by a process close to the normal process, a field effect transistor having a local shallow source/drain diffusion layer on both the sides of a gate electrode for self-matching operation and without etching damages, wherein impurities are ion-implanted onto the semiconductor side wall and onto the substrate surface of both the sides, and thermal treatment operation is effected so as to form the local shallow source/drain diffusing layers by the diffusion for activating the impurities of the deep shallow source drain diffusing layers, thereby to render to be capable of restraining a short channel effect and reducing the parasitic resistance of the semiconductor devices.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: February 21, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshimasa Matsuoka, Hiroshi Kotaki, Seizo Kakimoto
  • Patent number: 5028990
    Abstract: A semiconductor memory device having an improved storage capacitor is disclosed.
    Type: Grant
    Filed: April 13, 1989
    Date of Patent: July 2, 1991
    Assignee: NEC Corporation
    Inventors: Hiroshi Kotaki, Yasukazu Inoue
  • Patent number: 4987091
    Abstract: For making an inter-level insulating film between a capacitor electrode and a gate electrode mild at the shoulder portion thereof, a doped polysilicon film is overlain by a silicon oxide film on a dielectric film structure, and the silicon oxide film is slightly etched through an isotropical technique by using a mask layer for forming a hollow space with a generally quarter-circle configuration beneath the mask layer, then anisotropically etching the silicon oxide and the doped polysilicon by using the same mask layer, then depositing silicon oxide on the entire surface, then exposing the surface of a semiconductor substrate by using an etch-back technique for leaving the inter-level insulating film on the capacitor electrode, then forming a gate electrode on the inter-level insulating film.
    Type: Grant
    Filed: January 22, 1990
    Date of Patent: January 22, 1991
    Assignee: NEC Corporation
    Inventor: Hiroshi Kotaki
  • Patent number: 4977099
    Abstract: A method for fabricating a semiconductor memory device which includes a single substrate, at least one memory cell including at least one MOS transistor formed on the single substrate, and a peripheral circuit having at least one MOS transistor formed on the single substrate, comprises the steps of forming on the single substrate a gate electrode for each of the MOS transistors of the memory cell and the peripheral circuit, iono-implanting impurities at a low dosage by using the gate electrodes as a mask so as to forming a low impurity concentration of source/drain regions of the MOS transistors of the memory cell and the peripheral circuit, depositing a mask layer to cover an area of the memory cell, and ion-implanting impurities at a high dosage by using the mask layer as a mask, so as to dope impurities to only the source/drain regions of the MOS transistor of the peripheral circuit, so that the MOS transistor of the memory cell has the source/drain regions of a low impurity concentration, and the MOS tran
    Type: Grant
    Filed: October 31, 1989
    Date of Patent: December 11, 1990
    Assignee: NEC Corporation
    Inventor: Hiroshi Kotaki