Abstract: A data processing apparatus includes a shared buffer; an issuing unit that issues a write address for writing incoming data to the shared buffer; a receiving unit that receives a returned read address for the data read from the shared buffer; a monitoring buffer that saves information indicating use status of an address for the shared buffer; and a monitoring unit that monitors write address issuance and returned read address reception, changes the information for the write address, from an unused state to a used state, when the write address is issued, and changes the information for a read address to be returned, from a used state to an unused state when the returned read address is received. The monitoring unit determines the address for the shared buffer is overlapping, when the information for the write address indicates a used state when the write address is issued.

Abstract: A data processing apparatus includes a shared buffer; an issuing unit that issues a write address for writing incoming data to the shared buffer; a receiving unit that receives a returned read address for the data read from the shared buffer; a monitoring buffer that saves information indicating use status of an address for the shared buffer; and a monitoring unit that monitors write address issuance and returned read address reception, changes the information for the write address, from an unused state to a used state, when the write address is issued, and changes the information for a read address to be returned, from a used state to an unused state when the returned read address is received. The monitoring unit determines the address for the shared buffer is overlapping, when the information for the write address indicates a used state when the write address is issued.

Abstract: An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.

Abstract: In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.

Abstract: Provided is a test apparatus for testing a device under test, including a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals, a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe, and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

Abstract: Provided is a test apparatus for testing a device under test, comprising a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals; a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe; and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

Abstract: A data transmission apparatus includes an input interface; an output interface; and a first and second switch portions which are provided between the input interface and the output interface and which transfer a frame from the input interface to a destination output interface, wherein the first and the second switch portions each include a buffer which stores the frame from the input interface according to the destination output interface, a scheduler which reads the frame from the buffer and transfers the frame to the destination output interface, and a frame amount detection portion which detects the amount of frames held in the buffer according to the destination output interface, and the scheduler controls reading from the buffer based on difference between the held frame amount of the first switch portion and the held frame amount of the second switch portion which is detected by the frame amount detection portion.

Abstract: An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.

Abstract: In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.

Abstract: For providing a loop detection method and device which enables a general L2 switch to be applied and complicated condition equations or the like for determining a loop generation, a terminal moving state in which packets of a same transmitting source address are inputted to different ports is detected; a frequency of detecting the terminal moving state is counted for each port; and, when the frequency exceeds a threshold, it is regarded that a loop has occurred at the port.

Abstract: An e-mail apparatus enhancing the ease of operation. The e-mail messages are transmitted based on classification results to reduce the load of a user. The e-mail apparatus facilitates composing a body of a message, selecting registrant data for a prescribed area, selecting attributes and a setting for association with the body of the message, the attributes and the setting for determining a list of recipients of the message according to the registrant data in the prescribed area, and sending the message to the list of recipients.

Abstract: There is provided a memory testing apparatus capable of applying two address signals to a failure analysis memory in one test period, in the case that a memory under test operates in burst mode and adopts double data rate system. There is provided a burst address producing circuit 8 capable of producing two burst address signals in one test period, which comprises a clock-repetition-rate doubling circuit 15 for outputting a clock at twice the pulse repetition rate of the test period signal TI, a first multiplexer 16 for selecting either one of the clock TI and the rate-doubled clock from the circuit 15, and a burst address generating circuit for generating an address signal to be supplied to the failure analysis memory 5.

Abstract: A control mechanism of an automatic document feeder for an electrophotographic copying machine is provided with a plurality of document discharge trays and a selecting device to select one of the document discharge trays to receive a document which has been processed and discharged. The control mechanism generally selects a specified one of the document discharge trays when documents are set on a supply tray and transported sequentially by the feeder. Only while the first of these documents is being transported from the supply tray into a processing position, however, the control mechanism selects a tray other than the specified one such that a document which may have been left inadvertently in the feeder by the previous user does not become mixed with the documents which are discharged subsequently.