Patents by Inventor Hiroshi Matsumura

Hiroshi Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190214998
    Abstract: A delay locked loop circuit includes a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other, a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other, a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit, a first control circuit that outputs a first control signal that controls a time, and a second control circuit that outputs a second control signal.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo Soga, Kazuaki Oishi, Hiroshi Matsumura, Yoichi Kawano, Yasuhiro Nakasha
  • Publication number: 20190207646
    Abstract: A pulse position modulation circuit includes a delay path that includes a plurality of delay devices coupled in series with each other, a clock being passed through the plurality of delay devices, and a switching circuit that changes a time by which the clock is delayed in each of the plurality of delay devices according to input data.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo SOGA, Kazuaki Oishi, Hiroshi Matsumura, Yoichi Kawano, Yasuhiro Nakasha
  • Patent number: 10267382
    Abstract: The present invention relates to a V-ribbed belt to be wound around plural pulleys and used, including an extension layer that forms a back surface of the V-ribbed belt, a compression layer provided on one surface of the extension layer and having plural ribs extending parallel to each other along a longitudinal direction of the V-ribbed belt, and a load carrying cord embedded between the extension layer and the compression layer along the longitudinal direction of the V-ribbed belt, in which a distance from an outer peripheral portion of the load carrying cord on the rib side to a tip portion of the rib is from 2.0 to 2.6 mm, and a distance from the outer peripheral portion of the load carrying cord on the rib side to a bottom portion of the rib is from 0.3 to 1.2 mm.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 23, 2019
    Assignee: Mitsuboshi Belting Ltd.
    Inventors: Masashi Tamura, Hisato Ishiguro, Hiroshi Matsumura
  • Publication number: 20190068356
    Abstract: An impulse generation circuit includes a first impulse signal generation circuit configured to generate a first impulse signal based on a clock signal; a phase modulator configured to generate a second local signal by phase-modulating a first local signal; and a second impulse signal generation circuit configured to generate a second impulse signal by mixing the first impulse signal and the second local signal, the second impulse signal being a phase-modulated impulse signal.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 28, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Patent number: 10215256
    Abstract: The present invention relates to a V-ribbed belt to be wound around plural pulleys and used, including an extension layer that forms a back surface of the V-ribbed belt, a compression layer provided on one surface of the extension layer and having plural ribs extending parallel to each other along a longitudinal direction of the V-ribbed belt, and a load carrying cord embedded between the extension layer and the compression layer along the longitudinal direction of the V-ribbed belt, in which a distance from an outer peripheral portion of the load carrying cord on the rib side to a tip portion of the rib is from 2.0 to 2.6 mm, and a distance from the outer peripheral portion of the load carrying cord on the rib side to a bottom portion of the rib is from 0.3 to 1.2 mm.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: February 26, 2019
    Assignee: Mitsuboshi Belting Ltd.
    Inventors: Masashi Tamura, Hisato Ishiguro, Hiroshi Matsumura
  • Publication number: 20190025794
    Abstract: A machine learning device performs machine learning with respect to a numerical control device that operates a machine tool on the basis of a machining program. The machine learning device comprises a state information acquisition unit configured to acquire state information including conditions including conditions of a spindle speed, a feed rate, the number of cuts, and a cutting amount per one time or a tool compensation amount, and a cycle time of cutting a workpiece, and machining accuracy of the workpiece; an action information output unit configured to output action information including modification information of the condition; a reward output unit configured to output a reward value in reinforcement learning on the basis of the cycle time and the machining accuracy; and a value function updating unit configured to update an action value function on the basis of a reward value, the state information, and the action information.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 24, 2019
    Inventor: Hiroshi MATSUMURA
  • Patent number: 10108173
    Abstract: A numerical control device that controls servomotors configured to process a workpiece into an arbitrary finishing shape by performing a plurality of processing operations so that the tool moves along a processing locus, the numeral control device includes: an initial locus deriving unit configured to derive the processing locus based on the arbitrary finishing shape; a processed range acquiring unit configured to acquire a processed range in which the tool has performed the processing operation; a receiving unit configured to receive a processing instruction for a changed finishing shape different from the arbitrary finishing shape; and a changed locus deriving unit configured to derive a changed processing locus based on a shape of a changed processed part obtained by excluding the processed range from the changed finishing shape at the time of interruption of the processing.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 23, 2018
    Assignee: FANUC CORPORATION
    Inventors: Hiroshi Matsumura, Makoto Suzuki
  • Patent number: 9998170
    Abstract: An active phased array transmitter includes: a transmission frequency signal source that generates a transmission frequency signal; a modulator that modulates the transmission frequency signal based on transmission data and outputs the modulated transmission signal; a plurality of transmitters that change the phase and intensity of the modulated transmission signal; a transmission phased array antenna including a plurality of transmission antennas; a local transmission frequency signal source that generates a local transmission frequency signal; a first mixer that generates a first intermediate frequency transmission signal from a received signal of the radio waves output from the transmission antennas and the local transmission frequency signal; a second mixer that generates a second intermediate frequency transmission signal from the modulated transmission signal and the local transmission frequency signal; a transmission correlation processing circuitry that detects a transmission correlation relationship;
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: June 12, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Publication number: 20170366193
    Abstract: A programmable frequency divider includes a modulus frequency divider, a pulse counter, and a swallow counter. The pulse counter is configured to count an output signal from the modulus frequency divider, and output a frequency division signal, and the swallow counter is configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter. The programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 21, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Patent number: 9817106
    Abstract: A phased-array transmitter includes a first PLL for transmission, a control circuit, a plurality of transmission units, a delay circuit, and a second PLL for self-test. The first PLL is configured to generate a reference transmission signal, and the control circuit is configured to control the first PLL. The transmission units are configured to receive the reference transmission signal, and perform amplification and phase control to output unit transmission waves, respectively. The delay circuit is configured to delay a signal based on the reference transmission signal, and the second PLL is configured to receive an output signal of the delay circuit, and generate a self-test signal for performing self-test.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 14, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Publication number: 20170285606
    Abstract: A numerical control device that controls servomotors configured to process a workpiece into an arbitrary finishing shape by performing a plurality of processing operations so that the tool moves along a processing locus, the numeral control device includes: an initial locus deriving unit configured to derive the processing locus based on the arbitrary finishing shape; a processed range acquiring unit configured to acquire a processed range in which the tool has performed the processing operation; a receiving unit configured to receive a processing instruction for a changed finishing shape different from the arbitrary finishing shape; and a changed locus deriving unit configured to derive a changed processing locus based on a shape of a changed processed part obtained by excluding the processed range from the changed finishing shape at the time of interruption of the processing.
    Type: Application
    Filed: March 27, 2017
    Publication date: October 5, 2017
    Inventors: Hiroshi MATSUMURA, Makoto SUZUKI
  • Publication number: 20170260032
    Abstract: A component supplier of the present disclosure includes a magazine that stores pallets, a table that is provided in front of the magazine and is provided with a standby tables in multiple tiers in an up-and-down direction, a first lift that moves the table up and down, and a pallet supplier that is provided in front of the table and that includes a supply table which holds at least one of the pallets at a component supply position where the component is supplied. The table has a first placing and withdrawing unit that places and withdraws the pallet between the magazine and the standby tables and a second lift that moves the first placing and withdrawing unit up and down. The pallet supplier has a second placing and withdrawing unit that places and withdraws the pallet between the standby tables and the supply table.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 14, 2017
    Inventors: SYOZO KADOTA, HIROSHI MATSUMURA, KATSUHIKO ITOH, MAKOTO NAKASHIMA, TADASHI ENDO, HIROYUKI FUJIWARA
  • Publication number: 20170257137
    Abstract: An active phased array transmitter includes: a transmission frequency signal source that generates a transmission frequency signal; a modulator that modulates the transmission frequency signal based on transmission data and outputs the modulated transmission signal; a plurality of transmitters that change the phase and intensity of the modulated transmission signal; a transmission phased array antenna including a plurality of transmission antennas; a local transmission frequency signal source that generates a local transmission frequency signal; a first mixer that generates a first intermediate frequency transmission signal from a received signal of the radio waves output from the transmission antennas and the local transmission frequency signal; a second mixer that generates a second intermediate frequency transmission signal from the modulated transmission signal and the local transmission frequency signal; a transmission correlation processing circuitry that detects a transmission correlation relationship;
    Type: Application
    Filed: February 6, 2017
    Publication date: September 7, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Patent number: 9722314
    Abstract: A patch antenna includes: a substrate configured with a dielectric material; a ground electrode formed on one side surface of the substrate; and a radiation electrode having a rectangular shape formed on another side surface of the substrate, wherein a slit is formed in the radiation electrode in parallel to a first side of the radiation electrode to be shorter than the first side, and each of a gap between the slit and the first side and a gap between the slit and a second side facing the first side is shorter than the first side.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Matsumura, Yoichi Kawano
  • Patent number: 9614535
    Abstract: A PLL circuit includes a frequency divider dividing an oscillation signal to generate a divided signal having a cycle of T/M (M: an integer greater than one); a phase comparator generating M reference signals by sequentially delaying a reference signal having a cycle of T one after another by a predetermined delay time and generating an Exclusive OR calculation result of the M reference signals and the divided signal; a loop filter generating a voltage signal based on the Exclusive OR calculation result input thereto; a voltage-controlled oscillator generating the oscillation signal by oscillating at a frequency in accordance with the voltage signal; and a control circuit adjusting the predetermined delay time to be equal to T/2M based on an Exclusive OR calculation result of at least two of the M reference signals.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Patent number: 9548824
    Abstract: A receiver circuit includes: a local signal generation circuit that generates a local signal; and a test signal generation circuit that generates a test signal having a frequency close to a frequency of the local signal, wherein the test signal generation circuit includes an oscillator that generates the test signal, a mixer that mixes the local signal with an output of the oscillator to generate a low-frequency signal which is a difference signal between the local signal and the output of the oscillator, a phase detector that detects a phase difference between the low-frequency signal output by the mixer and a reference signal, and a filter that extracts a low-frequency component from an output of the phase detector, and controls an oscillation frequency of the oscillator by using an output of the filter.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Patent number: 9509058
    Abstract: A high-frequency module includes an integrated body including a semiconductor chip and a reflector, the semiconductor and the reflector being integrated by a resin; an antenna provided with a space from the reflector; and a rewiring layer provided on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to the antenna. Further, a method for manufacturing a high-frequency module, the method includes forming an integrated body by integrating a semiconductor chip with a reflector by a resin; and forming a rewiring layer on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to an antenna provided with a space from the reflector.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Matsumura, Daijiro Ishibashi, Toshihide Suzuki, Yoichi Kawano
  • Publication number: 20160344397
    Abstract: A lock detection circuit includes: a phase difference detection circuit that detects a phase difference between a divided signal of an oscillation signal and a reference signal; a differentiation circuit that calculates a second differential value and a third differential value of the phase difference; and a synchronization detect circuit that detects the reference signal synchronizes with the oscillation signal, based on the secondary differential value and the third differential value.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 24, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura
  • Patent number: 9497895
    Abstract: A pre-array temporary placement area A2 and a post-return temporary placement area A3 are set along with a lower receiving area A1. Temporary placement positions TP for lower receiving pins 22 in the pre-array temporary placement area A2 and the post-return temporary placement area A3 are previously assigned in consideration of requirements for preventing occurrence of interference between the lower receiving pins 22, which would otherwise occur during transfer of the lower receiving pins 22, and in accordance with array positions AP of the lower receiving pins 22 in the lower receiving area A1. Further, a transfer sequence is set in accordance with array positions AP.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 15, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shirou Yamashita, Hironori Kitashima, Tadashi Endo, Hiroshi Matsumura, Mie Morishima
  • Publication number: 20160269131
    Abstract: A receiver circuit includes: a local signal generation circuit that generates a local signal; and a test signal generation circuit that generates a test signal having a frequency close to a frequency of the local signal, wherein the test signal generation circuit includes an oscillator that generates the test signal, a mixer that mixes the local signal with an output of the oscillator to generate a low-frequency signal which is a difference signal between the local signal and the output of the oscillator, a phase detector that detects a phase difference between the low-frequency signal output by the mixer and a reference signal, and a filter that extracts a low-frequency component from an output of the phase detector, and controls an oscillation frequency of the oscillator by using an output of the filter.
    Type: Application
    Filed: January 21, 2016
    Publication date: September 15, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Matsumura