Abstract: In an air conditioner constructed to pass an air introduced into an air conditioning unit through an evaporator and a heater core both arranged in the unit, cooler pipes for the evaporator and heater pipes for the heater core are arranged to extend from the same side wall of the air conditioning unit.

Abstract: In an air conditioner constructed to pass an air introduced into an air conditioning unit through an evaporator and a heater core both arranged in the unit, cooler pipes for the evaporator and heater pipes for the heater core are arranged to extend from the same side wall of the air conditioning unit.

Abstract: In an air conditioner constructed to pass an air introduced into an air conditioning unit through an evaporator and a heater core both arranged in the unit, cooler pipes for the evaporator and heater pipes for the heater core are arranged to extend from the same side wall of the air conditioning unit.

Abstract: In an air conditioner constructed to pass an air introduced into an air conditioning unit through an evaporator and a heater core both arranged in the unit, cooler pipes for the evaporator and heater pipes for the heater core are arranged to extend from the same side wall of the air conditioning unit.

Abstract: In an air conditioner constructed to pass an air introduced into an air conditioning unit through an evaporator and a heater core, both arranged in the unit, cooler pipes for the evaporator and heater pipes for the heater core are arranged to extend from the same side wall of the air conditioning unit.

Abstract: In an air conditioner (1) constructed to pass an air introduced into an air conditioning unit (4) through an evaporator (33) and a heater core (34) both arranged in the unit (4), cooler pipes (90) for the evaporator (33) and heater pipes (91) for the heater core (34) are arranged to extend from the same side wall of the air conditioning unit (4).

Abstract: In an air conditioner (1) constructed to pass an air introduced into an air conditioning unit (4) through an evaporator (33) and a heater core (34) both arranged in the unit (4), cooler pipes (90) for the evaporator (33) and heater pipes (91) for the heater core (34) are arranged to extend from the same side wall of the air conditioning unit (4).

Abstract: A bipolar programmable read only memory device having improved data read speed is disclosed. Each of memory cells has one end connected to a reference potential point and the other end connected to a data write circuit so as to receive a programming current. A data read circuit is electrically isolated from the other end of each memory cell in a data write operation mode. In the data read operation mode, the memory cell is electrically coupled to the data read circuit.

Abstract: A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first and second additional row lines, a first diode connected between the first additional row line and one column line, a second diode connected between the second additional row line and another column line adjacent to the one column line, and a transistor of a base-open type connected between the second additional row line and the one column line.

Abstract: A signal generator which may be fabricated as monolithic integrated circuit is disclosed. The signal generator includes a counter having a plurality of stages and providing parallel outputs and a plurality of flip-flops. A programmable logic array capable of functioning as AND and OR logic and composed of a matrix arrangement of programmable elements receives as inputs the parallel outputs of the counter and provides inputs to the flip-flops to generate signals at the outputs of the flip-flops.

Abstract: An integrated circuit provided with at least one field-programmable element matrix which is reduced in size and improved in an electrical characteristics is disclosed. The circuit is characterized in that the matrix is physically divided into at least two separate parts, at least a part of a logic circuit for applying a logic input to the matrix or for receiving a logic output from the matrix in a read mode is disposed outside of the separate parts of the matrix, and at least a part of a selection circuit for writing or programming the matrix is disposed between the two divided parts of the matrix.

Abstract: A digital integrated circuit is provided with a maximum number of input and output terminals assigned for a normal operation mode and the number of terminals required for a function test is minimized. The integrated circuit is additionally provided with at least one control terminal, the functions of at least a part of the input and output terminals being determined in response to the logical level at the control terminal. Terminal utilization efficiency is further enhanced if the control terminal is connected to an inverter which is nonresponsive to the normal logic mode voltage range but which is responsive to a voltage outside the normal logic mode voltage range.

Abstract: An inverter circuit operating at a high speed and with low power consumption is disclosed, which comprises a first bipolar transistor having a collector coupled to the output of the circuit, a second bipolar transistor having a collector coupled to the base of the first transistor and means responsive to at least one input signal to produce a first signal for driving the first transistor and a second signal complementary to the first signal for driving the second transistor substantially at the same time.

Abstract: A read only memory integrated circuit includes a first group of transistors serving as the memory elements, and a second group of transistors in a memory peripheral circuit and integrated in the same substrate as the memory transistors. The base width of the first group of memory transistors is greater than that of the second group of transistors in the peripheral circuit.