Abstract: The disclosed merchandise tag is a non-contact wireless tag, has a color change layer on its surface, and the price data stored therein can be read out and rewritten. It can be easily attached and removed, reduces the amount of attachment implements used, and allows the display thereon to be easily changed by means of a heat treatment, magnetic treatment, or the like. The merchandise tag has an attachment hole 2 and a slit 3 that is formed to extend from the attachment hole up to the circumference of the merchandise tag, and contains a semiconductor integrated circuit, and one or more price data entries can be stored in the semiconductor integrated circuit. It preferably includes a rounded portion 4 at the intersection between the slit 3 and the circumference such that the angle formed between the slit 3 and the circumference is between 20 and 70 degrees.

Abstract: Articles entered into a sorting system are identified by means of an article identification device 1. An allocation ratio is selected from an allocation ratio table 7 based on the identifying information from the article identification device 1. Chute selection information is obtained for a sorter 2 based on the allocation ratio by means of a calculator 6, which in one embodiment uses a random number generator 8 to make a weighted calculation and a deviation reduction mechanism 11 to reduce the deviation of the accumulated weighted calculation results. A controller 3 selects a chute 4 such that the articles entered into the system will be distributed in accordance with the article allocation ratio, and provides the chute selection information to the sorter 2. The sorter 2, based upon the chute selection information, conducts sorting by dropping the articles entered into the system into the appropriate chute 4.

Abstract: The disclosed merchandise tag is a non-contact wireless tag, has a color change layer on its surface, and the price data stored therein can be read out and rewritten. It can be easily attached and removed, reduces the amount of attachment implements used, and allows the display thereon to be easily changed by means of a heat treatment, magnetic treatment, or the like. The merchandise tag has an attachment hole 2 and a slit 3 that is formed to extend from the attachment hole up to the circumference of the merchandise tag, and contains a semiconductor integrated circuit, and one or more price data entries can be stored in the semiconductor integrated circuit. It preferably includes a rounded portion 4 at the intersection between the slit 3 and the circumference such that the angle formed between the slit 3 and the circumference is between 20 and 70 degrees.

Abstract: Articles entered into a sorting system are identified by means of an article identification device 1. An allocation ratio is selected from an allocation ratio table 7 based on the identifying information from the article identification device 1. Chute selection information is obtained for a sorter 2 based on the allocation ratio by means of a calculator 6, which in one embodiment uses a random number generator 8 to make a weighted calculation and a deviation reduction mechanism 11 to reduce the deviation of the accumulated weighted calculation results. A controller 3 selects a chute 4 such that the articles entered into the system will be distributed in accordance with the article allocation ratio, and provides the chute selection information to the sorter 2. The sorter 2, based upon the chute selection information, conducts sorting by dropping the articles entered into the system into the appropriate chute 4.

Abstract: For one of memory divisions that is selected at a time as a selected division N(m) in a memory for use in putting a sound processing device in operation of generating a three-dimensional image of an acoustic field, a difference signal is produced to represent a clock count minus a delay count n(m) specific to the selected division and to have more and less significant bits. For use as an address signal supplied to the memory, a part of the more significant bits is changed to a like part of a memory space address specific to the selected division. As usual, the less significant bits are used to indicate read aR(i(m)) and write W(i(m)) pointers which are spaced in the selected division by the delay count. The part may be specified to be wide and narrow when the selected division is narrow and wide. Alternatively, the part may have a predetermined bit width.

Abstract: An output apparatus for image signals includes an image signal processing circuit for providing a digital luminance signal, a digital color signal, a digital composite video signal etc., a multiplexing circuit for multiplexing these signals to be positioned alternately on a time axis, a D/A converter for converting the digital multiplexed signal to an analog multiplexed signal, and plural signal holding circuits for an analog luminance signal, an analog color signal, an analog composite video signal etc. separated from the analog multiplexed signal, respectively. Therefore, only one D/A converter is used therein, so that the cost is decreased and the size becomes small.

Abstract: An analog-digital converting circuit comprises an analog amplifying circuit having different amplification factors and an input connected to an analog signal input terminal. A first selector is connected at a corresponding number of inputs to receive the plurality of amplified analog signals, respectively. The first selection circuit outputs one analog signal selected from the received amplified analog signals, to an analog-digital converter. A second selector is connected at its an input to receive a digital signal from the analog-digital converter and has a plurality of outputs for outputting the received digital signal from one sequentially alternatively selected from the plurality of outputs. A coefficient multiplying circuit is connected to the outputs of the second selector, and generates multiplied digital signals obtained by multiplying the outputs of the second selector by different coefficeints.

Abstract: A circuit for comparing first and second binary coded digital data signals has a plurality of first circuits each including first and second transistors of a P-channel type connected in series between a first potential terminal and a first output node, a plurality of second circuits each including third and fourth transistors of an N-channel type connected in series between a second potential terminal and a second output node, and means for precharging the first and second output nodes to first and second logic levels, respectively. The first and third transistors are supplied with one bit data of the first signal, and the second and fourth transistors are supplied with an inverted data of the second signal. A change in the logic level at least one of the first and second output nodes is detected.

Abstract: An integrated circuit having a signal terminal 13 and a reference terminal 14, an output transistor Q.sub.4 connected across these terminals with its gate or base connected to the output of exclusive OR gate 12, and an internal circuit 110 with its input port connected to the signal terminal and its output terminal connected to one of the inputs of the OR gate. The other OR-gate input is connected to the reference terminal. By applying the proper reference voltage to the reference terminal, the signal terminal can operate as an I/O terminal with another integrated circuit of the same or of different conductivity type.

Abstract: A charge transfer device in which a number of transfer electrodes, comprised of alternating main electrodes and auxiliary electrodes, are formed on but insulated from a channel region in a semiconductor substrate for transferring charges. The transfer electrodes are formed such that the sides of each of the electrodes which are transverse to the channel direction are concave in the direction of charge transfer. These concave sides produce an additional accelerating electric field which supplements the conventional fringing fields.

Abstract: A counter for counting pulses or dividing frequencies has a timing signal generator circuit for generating a timing signal at a predetermined interval. A hysteresis circuit has input-output characteristics defining a low input threshold level and a high input threshold level. A control circuit responds to the timing signal for generating at least three control signals having different levels including a first control signal having a level lower than the low input threshold level, a second control signal having a level higher than the high input threshold level, and a third control signal having an intermediate level which is between the low input threshold level and the high input threshold level. The counter has a very large capacity, simple construction, and is effective with both analog and digital signals.

Abstract: A digital vertical synchronization system for use in a television receiver is disclosed. A vertical synchronization separator circuit receives a composite synchronizing signal and separates a vertical synchronizing signal from the composite signal. A clock counter receives a clock input signal having a frequency equal to a positive integer N times as high as the frequency of a horizontal synchronizing signal separated from the composite signal. The clock counter produces a first output signal having a repetition frequency substantially equal to the vertical synchronizing signal and having a pulse width required for generating a vertical deflection signal and a second output signal having a pulse width equal to or smaller than the pulse width of the vertical synchronizing signal. A phase comparator compares the phases of the second output signal of the clock counter and the vertical synchronizing signal and produces a reset signal when the phases of the two signals are not coincident.

Abstract: A signal detector circuit comprises a plurality of series-connected data latch circuits. An input signal and clock signals are applied to the first data latch circuit, the clock signals being effective to shift the input signal along the succeeding data latch circuits. The outputs of the data latch circuits are coupled to the plural inputs of a plurality of first logic circuits in a manner such that the outputs of different data latch circuits are combined at different ones of the first logic circuits. The outputs of the first logic circuits are combined in a second logic circuit which produces an output signal. The input signal may be a composite television synchronizing signal and the output signal may correspond to the vertical sync pluses in the composite synchronizing signal.