Patents by Inventor Hiroshi Nada

Hiroshi Nada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11674997
    Abstract: A test system is disclosed. The test system includes a programmable switching array including input terminals, output terminals, and an array of programmable switches configured for selectively connecting any one of the input terminals to any one of output terminals; and a current supply device comprising a multiplexed digital bus and a plurality of a power supplies connected in parallel between the multiplexed digital bus and the input terminals of the programmable switching array.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: June 13, 2023
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventors: Ken Yawata, Hiroshi Nada
  • Patent number: 11619666
    Abstract: A measurement apparatus includes external terminals configured for connection to a device-under-test (DUT), the external terminals including first and second force terminals and first and second sense terminals. The measurement apparatus further includes a controller and a feedback loop configured in a current feedback mode to sense a current flowing from the first force terminal to the second force terminal, and in a voltage feedback mode to sense a voltage across the first and second sense terminals. The measurement apparatus further includes a measurement path configured to measure a least one of a voltage and current across a pair of the external terminals and to supply the measured at least one of the voltage and current to the controller.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 4, 2023
    Assignee: Keysight Technologies, Inc.
    Inventors: Nobuaki Iwaki, Yasuhiro Miyake, Masaki Sato, Hiroshi Nada
  • Publication number: 20220236319
    Abstract: A test system is disclosed. The test system includes a programmable switching array including input terminals, output terminals, and an array of programmable switches configured for selectively connecting any one of the input terminals to any one of output terminals; and a current supply device comprising a multiplexed digital bus and a plurality of a power supplies connected in parallel between the multiplexed digital bus and the input terminals of the programmable switching array.
    Type: Application
    Filed: April 19, 2022
    Publication date: July 28, 2022
    Inventors: Ken Yawata, Hiroshi Nada
  • Patent number: 11333701
    Abstract: A current supply device includes a multiplexed digital bus, an output terminal, and a group of power supplies connected in parallel between the multiplexed digital bus and the output terminal. The group of power supplies are controlled via the multiplexed digital bus such that a combined output current of the group of power supplies is applied to the output terminal.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 17, 2022
    Assignee: Keysight Technologies, Inc.
    Inventors: Ken Yawata, Hiroshi Nada
  • Publication number: 20210231728
    Abstract: A current supply device includes a multiplexed digital bus, an output terminal, and a group of power supplies connected in parallel between the multiplexed digital bus and the output terminal. The group of power supplies are controlled via the multiplexed digital bus such that a combined output current of the group of power supplies is applied to the output terminal.
    Type: Application
    Filed: January 27, 2020
    Publication date: July 29, 2021
    Inventors: Ken Yawata, Hiroshi Nada
  • Patent number: 9651596
    Abstract: Systems and methods for determining a capacitance on a device-under-test (“DUT”). An example implementation includes a voltage signal generator that generates a voltage signal alternating between a high voltage and a low voltage at regular time intervals. The voltage signal generator causes a DUT current to flow in the DUT. The DUT current comprises a leakage current and a capacitance measurement current in response to the voltage signal. A current signal generator receives the DUT current from the DUT. The current signal generator generates a cancellation current signal alternating between high and low values at the regular time intervals of the voltage signal such that the cancellation current signal cancels the leakage current through the DUT. A signal measurement circuit receives the capacitance measurement current remaining after the leakage current is canceled to generate an output voltage having an output voltage value used to determine a capacitance of the DUT.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 16, 2017
    Assignee: Keysight Technologies, Inc.
    Inventors: Kenichi Takano, Hiroshi Nada
  • Publication number: 20150061720
    Abstract: Systems and methods for determining a capacitance on a device-under-test (“DUT”). An example implementation includes a voltage signal generator that generates a voltage signal alternating between a high voltage and a low voltage at regular time intervals. The voltage signal generator causes a DUT current to flow in the DUT. The DUT current comprises a leakage current and a capacitance measurement current in response to the voltage signal. A current signal generator receives the DUT current from the DUT. The current signal generator generates a cancellation current signal alternating between high and low values at the regular time intervals of the voltage signal such that the cancellation current signal cancels the leakage current through the DUT. A signal measurement circuit receives the capacitance measurement current remaining after the leakage current is canceled to generate an output voltage having an output voltage value used to determine a capacitance of the DUT.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Kenichi Takano, Hiroshi Nada
  • Patent number: 7812619
    Abstract: A capacitance measuring apparatus which comprises: a voltage source for applying voltage fluctuation to a device under test; a current source for absorbing the current flowing through the resistance component of the device under test; and an ammeter for measuring the leakage current flowing through the device under test before and after voltage fluctuation and the charging current flowing through the device under test as a result of voltage fluctuation.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: October 12, 2010
    Assignee: Agilent Technologies, Inc.
    Inventors: Shinichi Tanida, Hiroshi Nada, Tomoe Ikawa
  • Publication number: 20090267634
    Abstract: A switch module is disclosed for semiconductor characteristic measurement and a semiconductor characteristic measurement method is disclosed with which the impact of the recovery effect after stress signal elimination is reduced in BTI testing. The switch module for semiconductor characteristic measurement includes a first input terminal for receiving stress signals from a stress signal source, a second input terminal for receiving signals from a first non-stress signal source, a first output terminal for outputting output signals, and a switch part for controlling the connection of the first output terminal and the first input terminal or the second input terminal, wherein the switch part detects a first voltage transition of the signals transmitted to the second input terminal and modifies the connection.
    Type: Application
    Filed: November 28, 2008
    Publication date: October 29, 2009
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Hiroshi Nada, Yoichi Kuboyama, Atsushi Mikata
  • Publication number: 20080068029
    Abstract: A capacitance measuring apparatus which comprises: a voltage source for applying voltage fluctuation to a device under test; a current source for absorbing the current flowing through the resistance component of the device under test; and an ammeter for measuring the leakage current flowing through the device under test before and after voltage fluctuation and the charging current flowing through the device under test as a result of voltage fluctuation.
    Type: Application
    Filed: August 9, 2007
    Publication date: March 20, 2008
    Inventors: Shinichi Tanida, Hiroshi Nada, Tomoe Ikawa
  • Publication number: 20060208754
    Abstract: A method for a reliability testing of a device under test which comprises: a first step for applying a second voltage after applying for a predetermined time a first voltage to a device under test and measuring the current flowing through the device under test; a second step for conducting the first step on the same device under test two or more consecutive times; a third step for conducting in succession the second step on a plurality of devices under test; a fourth step for conducting the first step on the same device under test, once or two or more consecutive times; a fifth step for conducting in succession the fourth step on a plurality of devices under test after conducting the third step; and a sixth step for finding the relationship between the total time for which the first voltage has been applied and the current for each device under test, and an apparatus that uses this method.
    Type: Application
    Filed: December 22, 2005
    Publication date: September 21, 2006
    Inventors: Yasuhiro Takeuchi, Hiroshi Nada
  • Patent number: 5285151
    Abstract: A ramp voltage is applied through a current limiter 2 to a DUT 3. Setting as a reference time point (t.sub.1) a time when a ramp portion of the response voltage V of the DUT 3 has settled to a prescribed value (for example, when the voltage gradient is reduced by a predetermined rate to the ramp rate RR/2), the measurement is carried out, at time t.sub.2, after a predetermined interval from the reference time t.sub.2. Accordingly, a breakdown voltage is measured before the response voltage V of the DUT 3 is influenced by heat, etc., power consumption is reduced and an excessive stress is not applied to the DUT 3, so that no damage or burning occurs in the DUT 3.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: February 8, 1994
    Assignee: Hewlett-Packard Company
    Inventors: Hideo Akama, Hiroshi Nada