Abstract: A semiconductor storage device includes: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change.

Abstract: A semiconductor memory device includes a memory cell array provided with blocks each having a plurality of memory cells arranged in columns and rows, a column selection circuit selecting a column via bit lines based on a column section signal, a word line driver circuit selecting a row via a word line based on a row selection signal and the column selection signal, and a write/read circuit writing data to and reading data from a selected memory cell via the bit lines based on a write and read switching signal. The selected memory cell is arranged at a position determined by the column selected by the column selection circuit and the row selected by the word line driver circuit within one block. Rows corresponding to the blocks are provided in common with the same number of word lines as the columns, and the memory cells arranged in one row within one block are coupled to mutually different word lines.

Abstract: A semiconductor memory device includes a memory cell array provided with blocks each having a plurality of memory cells arranged in columns and rows, a column selection circuit selecting a column via bit lines based on a column section signal, a word line driver circuit selecting a row via a word line based on a row selection signal and the column selection signal, and a write/read circuit writing data to and reading data from a selected memory cell via the bit lines based on a write and read switching signal. The selected memory cell is arranged at a position determined by the column selected by the column selection circuit and the row selected by the word line driver circuit within one block. Rows corresponding to the blocks are provided in common with the same number of word lines as the columns, and the memory cells arranged in one row within one block are coupled to mutually different word lines.

Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.

Abstract: The address decoder includes: a plurality of decode units each formed by a combinational logic circuit; an inverting circuit which inverts an output of said decode unit; an AND circuit which performs a logical AND operation between an output signal of said decode unit, which has been inverted by said inverting circuit, and another one of said plurality of decode units. This arrangement makes it possible to simplify the circuit construction, to improve the processing speed, and to reduce power consumption.

Abstract: The address decoder includes: a plurality of decode units each formed by a combinational logic circuit; an inverting circuit which inverts an output of said decode unit; an AND circuit which performs a logical AND operation between an output signal of said decode unit, which has been inverted by said inverting circuit, and another one of said plurality of decode units. This arrangement makes it possible to simplify the circuit construction, to improve the processing speed, and to reduce power consumption.

Abstract: For the purpose of providing an inexpensive memory from which test results can be certainly read out, a semiconductor device having a BIST circuit (built-in self test circuit) includes a RAM for use in processing to be tested incorporated in a data processing system, a built-in self test circuit making a built-in self test on the RAM for use in processing, and a RAM for tester storing test results of the RAM for use in processing obtained by the built-in self test circuit so that the test results can be read out by an external tester, wherein a RAM having a data read-out margin greater than a data read-out margin of the RAM for use in processing is used as the RAM for tester.

Abstract: For the purpose of providing an inexpensive memory from which test results can be certainly read out, a semiconductor device having a BIST circuit (built-in self test circuit) comprises a RAM for use in processing to be tested incorporated in a data processing system, a built-in self test circuit making a built-in self test on the RAM for use in processing, and a RAM for tester storing test results of the RAM for use in processing obtained by the built-in self test circuit so that the test results can be read out by an external tester, wherein a RAM having a data read-out margin greater than a data read-out margin of the RAM for use in processing is used as the RAM for tester.

Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.