Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Abstract: A compressing/expanding circuit for compressing and expanding image data by a JBIG method comprises a memory medium such as floppy disk or hard disc to store the image data, a compressing circuit to compress the data, an expanding circuit to expand the data, a transfer circuit to transfer the data stored in the memory medium to the compressing circuit or expanding circuit, a storage controller to store the data compressed by the compressing circuit or the data expanded by the expanding circuit to the memory medium, a compression controller to control the transfer circuits compressing circuit, and storage controller so as to repetitively operate, an expansion controller to control the transfer circuit, expanding circuit, and storage controller so as to repetitively operate, and a designating circuit to designate either one of the compressing process and the expanding process.

Abstract: Disclosed is a method of processing image data, including controlling to output multi-level value image data for reproducing a multi-level value image and bi-level value image data for reproducing a bi-level value image with respect to a predetermined area, thereby reproducing the multi-level and bi-level value images which constitute a single image.

Abstract: An image processing apparatus makes it possible to efficiently use memories, and to output an image having a high picture quality and a high resolution. The apparatus also makes it possible to reproduce particularly edge portions of an image having a relatively low resolution wherein a plurality of bits are allocated per picture element, with a high resolution. The apparatus further makes it possible to reproduce an image having a high resolution represented by one bit per picture element as an image represented by a plurality of bits per picture element. The apparatus processes a color image obtained by synthesizing a photograph and another photograph, or a photograph and characters with a small memory capacity, and outputs an image having a high quality.

Abstract: A display control apparatus for a display apparatus having a display device in which a liquid crystal such as a ferroelectric liquid crystal is used as an operating medium for display-updating and the updated display state can be held by applying an electric field or the like. The display control apparatus comprises a first updating circuit to update the display content of the entire screen of the display apparatus, a second updating circuit to update the display content of a part of the display screen, a detector to detect an external factor such as a temperature of the display apparatus, and a switching circuit to switch the first and second updating circuits in accordance with the detected external factor.

Abstract: A preserving performance of a display state of a display having a ferroelectric liquid crystal (FLC) as a display device is effectively used, thereby realizing a long life of the display. For this purpose, access monitor device is provided. The access of a video memory by display data supply device is monitored. When there is no access for a predetermined time or more, that is, when there is no change in the present display content, display drive control device controls display driving device so as to stop the driving of an FLC panel.

Abstract: An image processing apparatus is arranged to store different types of image data containing color information so as to provide an image output, hold in a register display information corresponding to each of these types of stored image data, classifying the stored image data on the basis of the display information held in the register, and generate pixel data on the basis of the classified image data.

Abstract: In a data processing system that includes plural image processing apparatus and a network connecting these apparatus, reduced image data in the disk 11 of the work station WS4 are transferred through the LAN 6 to the work station WS1. The work station WS1 edits the transferred reduced image data and transfers the content of editing alone through the LAN 6 to the work station WS4, which regenerates the original image from the transferred content of editing, the reduced image data and the encoded data, and prints the original image in edited state.

Abstract: Display drive of a ferroelectric liquid crystal (FLC) display device is controlled in accordance with temperature and the number of lines to be displayed and updated. An interlace or non-interlace mode for driving the display device is selected on the basis of the number of scanning lines to be updated and/or the temperature. A table is provided for changing the interlace mode on the basis of various conditions.

Abstract: A display control apparatus and method initializes the display when the power is switched off. The display control apparatus includes a storing unit which corresponds to a display panel and stores display data, a display control unit for achieving an image on the display panel in accordance with the data stored in the storing unit, a detecting unit for detecting disconnection of a power source, and an initializing unit for initializing the storing unit when the detecting unit has determined that the power source is disconnected. The display control method performs display by using information stored in a memory corresponding to the display panel. The method is carried out by detecting a request for power disconnection, writing initialization data into the memory, achieving an image on the display panel by using the initialization data written in the memory, and disconnecting the power.

Abstract: There is disclosed an image processing system with variable gamma characteristic, in which gamma correction is not conducted in the image processing but conducted for the output equipment when the result of image processing is released outside.

Abstract: A display control device for a display unit, using a ferroelectric liquid crystal or the like, capable of partially changing a display state of picture elements is provided with an entire updating means for updating a display of the entire picture surface of the display unit. A partial updating means is provided for updating only a portion wherein display contents have changed during entirely updating processing. A restriction means restricts the start of the partially updating means in accordance with a frequency of a command to update the portion.

Abstract: Disclosed is a method of processing image data, including controlling to output multi-level value image data for reproducing a multi-level value image and bi-level value image data for reproducing a bi-level value image with respect to a predetermined area, thereby reproducing the multi-level and bi-level value images which constitute a single image.

Abstract: An image processing apparatus is disclosed which includes circuitry for selectively applying variable gamma corrections to an image signal during both on-line and off-line modes of operation. In the off-line mode, the apparatus operates to simultaneously correct image signals for non-linearities produced by both an input device and an output device. In the on-line mode, correction is made for the non-linearities of the input device and a separate correction is made for the non-linearities of the output device. Such operation allows the apparatus to process linear data in the on-line mode.

Abstract: A display control device for a display unit, using a ferroelectric liquid crystal or the like, capable of partially changing a display state of picture elements is provided with an entire updating means for updating a display of the entire picture surface of the display unit. A partial updating means is provided for updating only a portion in which display contents have changed during entire updating processing. A restriction means restricts the start of operation of the partial updating means in accordance with whether the number of lines to be updated exceeds a predetermined number, where the predetermined number is less than the total number of line in the display unit.

Abstract: An image processing apparatus is disclosed which inputs/outputs an image in which image data items having different quantities of information for each pixel are mixed with one another. The information quantity for each of the image data items and information about the I/O positions are stored in a corresponding manner. When data is input, data is converted into the proper information quantities in accordance with input position, for storage. When data is output, the stored image data is converted into output data in accordance with the respective information quantities. As a result, the memory capacity can be reduced, the flexibility can be improved at the time of use and the memory can be used efficiently.

Abstract: An image processing apparatus includes input circuitry for inputting an analog video signal, first conversion circuitry for converting the input analog video signal into multi-value data, and a memory for storing the multi-value data. Second conversion circuitry is provided for converting the multi-value data stored in the memory to binary data when executing its conversion process. The second conversion circuitry (1) detects a density gradient by comparing the multi-value data of pixels around a pixel to be converted with each other in each of vertical, lateral, and oblique directions, and (2) selects a multi-bit image pattern from a plurality of image patterns in response to the detected density gradient.