Patents by Inventor Hiroshi OGURI

Hiroshi OGURI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240092337
    Abstract: A vehicle control apparatus includes front-wheel and rear-wheel driving systems, and a control system. The front-wheel driving system includes a first travel motor mechanically coupled to a front wheel of a vehicle and a first accumulator electrically coupled to the first travel motor. The rear-wheel driving system includes a second travel motor mechanically coupled to a rear wheel of the vehicle and a second accumulator electrically coupled to the second travel motor. The control system includes one or more processors and one or more memories communicably coupled to the one or more processors, and controls the first and second travel motors. When a difference between an SOC of the first accumulator and an SOC of the second accumulator is greater than a threshold value, the one or more processors change a torque distribution ratio between the first and second travel motors from a reference distribution ratio.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 21, 2024
    Inventors: Hiroshi KUSANO, Yoshinobu YAMAZAKI, Masami OGURI, Akihiro NABESHIMA, Yoshiyuki JIN, Takeshi YONEDA, Fumiya SATO, Keigo YAMADA, Takumi ARAKI, Shuntaro MIURA
  • Patent number: 11914315
    Abstract: In a caser where a first current is supplied to a first heater, a controller gradually increases the first current in a first period, supplies the first current based on a first duty cycle in a second period, and gradually reduces the first current to stop supplying the first current in a third period. In a case where a second current is supplied to a second heater, the controller gradually increases the second current in a fourth period, supply the second current based on a second duty cycle in a fifth period, and gradually reduces the second current to stop supplying the second current in a sixth period. The controller controls the supply of the second current such that part of the fourth period overlaps with the third period.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: February 27, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Oguri
  • Publication number: 20230025489
    Abstract: In a caser where a first current is supplied to a first heater, a controller gradually increases the first current in a first period, supplies the first current based on a first duty cycle in a second period, and gradually reduces the first current to stop supplying the first current in a third period. In a case where a second current is supplied to a second heater, the controller gradually increases the second current in a fourth period, supply the second current based on a second duty cycle in a fifth period, and gradually reduces the second current to stop supplying the second current in a sixth period. The controller controls the supply of the second current such that part of the fourth period overlaps with the third period.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 26, 2023
    Inventor: Hiroshi Oguri
  • Publication number: 20170200693
    Abstract: An electronic component includes a base, a laminate of a plurality of conductive metal material layers, and a solder layer made of Au—Sn alloy solder. The laminate is disposed on the base. The solder layer is disposed on the laminate. The laminate includes a surface layer made of Au as the conductive metal material layer constituting an outermost layer. The surface layer includes a solder layer-disposing region in which the solder layer is disposed and a solder layer-empty region in which the solder layer is not disposed. The solder layer-disposing region and the solder layer-empty region are spatially separated from each other.
    Type: Application
    Filed: August 5, 2015
    Publication date: July 13, 2017
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshimaro FUJII, Hiroshi OGURI, Akira SAKAMOTO, Tomoya TAGUCHI
  • Patent number: 9385151
    Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 5, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
  • Publication number: 20150171127
    Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions
    Type: Application
    Filed: February 20, 2015
    Publication date: June 18, 2015
    Inventors: Hiroshi OGURI, Yoshitaka ISHIKAWA, Akira SAKAMOTO, Tomoya TAGUCHI, Yoshimaro FUJII
  • Patent number: 8993361
    Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 31, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
  • Publication number: 20140061840
    Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroshi OGURI, Yoshitaka ISHIKAWA, Akira SAKAMOTO, Tomoya TAGUCHI, Yoshimaro FUJII