Patents by Inventor Hiroshi Ohta

Hiroshi Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8872261
    Abstract: A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third diffusion layers are the same.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Irifune, Wataru Saito, Yasuto Sumi, Kiyoshi Kimura, Hiroshi Ohta, Junji Suzuki
  • Patent number: 8860144
    Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
  • Publication number: 20140290220
    Abstract: An engine unit includes an engine, an exhaust gas treatment device and a connecting pipe. The engine has an exhaust gas port. The exhaust gas treatment device is arranged above the engine. The connecting pipe connects the exhaust gas port and the exhaust gas treatment device. The connecting pipe has an expandable-contractible bellows portion. The bellows portion has a linear form following the upward-downward direction. The lower end portion of the bellows portion is positioned lower than at least a part of the exhaust gas port.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: KOMATSU LTD.
    Inventors: Taira Ozaki, Hiroshi Nakagami, Hironori Yamamitsu, Kanji Namimatsu, Hiroshi Ohta, Kenji Matsubara
  • Publication number: 20140290781
    Abstract: An exhaust gas treatment unit includes an exhaust gas treatment device, a bracket and a connecting pipe. The exhaust gas treatment device is mounted on a bracket. The connecting pipe is connected to the exhaust gas treatment device. The connecting pipe directs exhaust gas to the exhaust gas treatment device. The connecting pipe may include a supporting portion and a pipe portion, with the supporting portion supporting the bracket and the pipe portion being integrated with the supporting portion. Alternatively, the exhaust gas treatment unit may further include a supporting member having a supporting portion supporting the bracket and a pipe portion integrated with the supporting portion, with the pipe portion connected to the connecting pipe.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: KOMATSU LTD.
    Inventors: Taira Ozaki, Hiroshi Nakagami, Hironori Yamamitsu, Kanji Namimatsu, Hiroshi Ohta, Kenji Matsubara
  • Publication number: 20140284756
    Abstract: A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.
    Type: Application
    Filed: May 7, 2014
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Syotaro ONO, Masaru IZUMISAWA, Hiroshi OHTA, Hiroaki YAMASHITA
  • Publication number: 20140227581
    Abstract: Disclosed is a cell including: a closed-end tubular case for accommodating a power generation element; a lid for the case; a terminal electrode disposed outside of the case and used for connection with another cell; an extraction electrode passing through the lid and used to extract power of the power generation element to the outside of the case; and a stepped connection electrode disposed outside of the case, the stepped connection electrode having a first flat portion to which the terminal electrode is connected and a second flat portion which is located at a level different from the level of the first flat portion and to which the extraction electrode is connected. The first and second flat portions have regions overlapping each other as viewed in a direction orthogonal to the thickness of the first and second flat portions.
    Type: Application
    Filed: August 29, 2011
    Publication date: August 14, 2014
    Inventor: Hiroshi Ohta
  • Publication number: 20140228377
    Abstract: A compound represented by formula (IA) or a pharmaceutically acceptable salt thereof, which acts relying on an orexin (OX) receptor antagonistic activity and is useful for the treatment or prevention of diseases such as sleep disorder, depression, anxiety disorder, panic disorder, schizophrenia, drug dependence, Alzheimer's disease, Parkinson's disease, Huntington's chorea, eating disorder, head ache, migraine, pain, gastrointestinal diseases, epilepsy, inflammations, immune-related diseases, endocrine-related diseases and hypertension.
    Type: Application
    Filed: July 4, 2012
    Publication date: August 14, 2014
    Applicant: TAISHO PHARMACEUTICAL CO., LTD.
    Inventors: Masahito Abe, Aya Futamura, Ryo Suzuki, Dai Nozawa, Hiroshi Ohta, Yuko Araki
  • Patent number: 8796272
    Abstract: The present invention relates to novel compounds of formula [I] or pharmaceutically acceptable salts thereof: The compounds of the present invention are useful in the prevention or treatment of diseases such as schizophrenia, Alzheimer's disease, cognitive impairment, dementia, anxiety disorders (e.g., generalized anxiety disorder, panic disorder, obsessive-compulsive disorder, social anxiety disorder, post-traumatic stress disorder, specific phobias, acute stress disorder), depression, drug dependence, spasm, tremor, pain, Parkinson's disease, attention deficit hyperactivity disorder, bipolar disorder, eating disorder, or sleep disorders, which is based on the glycine uptake-inhibiting action.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 5, 2014
    Assignee: Taisho Pharmaceutical Co., Ltd
    Inventors: Minoru Moriya, Hiroshi Ohta, Shuji Yamamoto, Kumi Abe, Yuko Araki, Xiang-Min Sun, Daisuke Wakasugi
  • Publication number: 20140191310
    Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 10, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Syotaro ONO, Masaru IZUMISAWA, Hiroshi OHTA, Hiroaki YAMASHITA
  • Patent number: 8759938
    Abstract: A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
  • Patent number: 8748025
    Abstract: In a cell holding device, engaging members (224) are disposed in an insertion cavity (222) into which an end portion of each cell (400) is inserted, such that the engaging members (224) are movable in a direction of insertion in which the cell (400) is inserted. The cell holding device also has guides (225) that push the engaging members (224) toward the inner radius of the insertion cavity (222) as the engaging members (224) move in the direction of insertion. With this arrangement, when the end portion of the cell (400) is inserted into the insertion cavity (222), the engaging members (224) sandwiched between the guides (225) and a side circumferential surface (403) of the cell (400) hold the end portion of the cell (400).
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: June 10, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hiroshi Ohta
  • Patent number: 8734126
    Abstract: A screw compressor includes a low pressure stage compressor body; a high pressure stage compressor body that further compresses a compressed air compressed by the low pressure stage compressor body; pinion gears for example, respectively, provided on, for example, a male rotor of the low pressure stage compressor body and, for example, a male rotor of the high pressure stage compressor body; a motor; a bull gear for example, provided on a rotating shaft of the motor; and an intermediate shaft supported rotatably and provided with a pinion gear, which meshes with the bull gear, and a bull gear, which meshes with the pinion gears. Thereby, it is possible to make the motor relatively low in rotating speed while inhibiting the gears from being increased in diameter, thus enabling achieving reduction in cost.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 27, 2014
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Hitoshi Nishimura, Tomoo Suzuki, Hiroshi Ohta
  • Patent number: 8729271
    Abstract: The present invention aims to provide novel compounds of formula [I] or pharmaceutically acceptable salts thereof that are based on a glycine uptake inhibiting action and which are useful in the prevention or treatment of such diseases as schizophrenia, Alzheimer's disease, cognitive dysfunction, dementia, anxiety disorders (generalized anxiety disorder, panic disorder, obsessive-compulsive disorder, social anxiety disorder, posttraumatic stress disorder, specific phobia, acute stress disorder, etc.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 20, 2014
    Assignee: Taisho Pharmaceutical Co., Ltd
    Inventors: Minoru Moriya, Akito Yasuhara, Kazunari Sakagami, Hiroshi Ohta, Kumi Abe, Shuji Yamamoto, Yuko Araki, Hiroki Urabe, Xiang-Min Sun
  • Patent number: 8716789
    Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
  • Publication number: 20140117445
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.
    Type: Application
    Filed: December 23, 2013
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyoshi KIMURA, Yasuto SUMI, Hiroshi OHTA, Hiroyuki IRIFUNE
  • Patent number: 8680606
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune
  • Publication number: 20140081025
    Abstract: The compound represented by formula (IA) or a pharmaceutically acceptable salt thereof is based on orexin (OX) receptor antagonist activity, is useful in the treatment and prevention of illnesses including sleep disorder, depression, anxiety disorder, panic disorder, schizophrenia, drug dependency, Alzheimer's disease, Parkinson's disease, Huntington's chorea, eating disorders, pain, gastrointestinal disease, epilepsy, inflammation, immunological disease, endocrinological related disease, and hypertension.
    Type: Application
    Filed: May 8, 2012
    Publication date: March 20, 2014
    Applicant: TAISHO PHARMACEUTICAL CO., LTD.
    Inventors: Ryo Suzuki, Aya Futamura, Masahito Abe, Shuhei Kashiwa, Nobutaka Hattori, Dai Nozawa, Hiroshi Ohta, Yuko Araki
  • Publication number: 20140077254
    Abstract: A semiconductor device includes an element region and an end region, the element region having a semiconductor element formed therein, and the end region surrounding the element region. The semiconductor device includes a semiconductor substrate, a trench, an insulating layer, and a field plate conductive layer. The trench is formed in the semiconductor substrate so as to surround the element region in the end region. The field plate conductive layer is formed in the trench via the insulating layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru IZUMISAWA, Syotaro ONO, Hiroshi OHTA, Hiroaki YAMASHITA
  • Patent number: 8643056
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi Kimura, Yasuto Sumi, Hiroshi Ohta, Hiroyuki Irifune
  • Patent number: 8642626
    Abstract: Provided is a novel compound represented by formula [I] or a pharmaceutically acceptable salt thereof having antagonistic activity against group II metabolism-type glutamic acid (m-Glu) receptors. The compound or pharmaceutically acceptable salt thereof is useful as a prophylactic or therapeutic agent for diseases such as new mood disorders (depressive and bipolar disorders), anxiety disorders (generalized anxiety disorder, panic disorder, obsessive-compulsive disorder, social anxiety disorder, post-traumatic stress disorder, specific phobias, and acute stress disorder), schizophrenia, Alzheimer's disease, cognitive dysfunction, dementia, drug dependence, convulsions, tremors, pain, sleep disorders, and the like.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: February 4, 2014
    Assignee: Taisho Pharmaceutical Co., Ltd.
    Inventors: Toshio Nakamura, Kazunari Sakagami, Kazuhide Konishi, Kanako Yamamoto, Seiji Masuda, Yohei Matsuda, Kumiko Okada, Tsuyoshi Shibata, Hiroshi Ohta, Akito Yasuhara, Hiroshi Kawamoto