Patents by Inventor Hiroshi Okano
Hiroshi Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140082332Abstract: A semiconductor integrated circuit includes: a floating point arithmetic unit that includes circuit resources over which power saving control is performed, and executes a floating point arithmetic operation; a power-control instruction control unit that receives a pre-access instruction corresponding to a floating point arithmetic operation instruction, and invalidates stepwise the power saving control over the circuit resources included in the floating point arithmetic unit to operate a part of the circuit resources in the floating point arithmetic unit; and a control unit that causes the floating point arithmetic unit to execute the floating point arithmetic operation, wherein before execution of the floating point arithmetic operation in the floating point arithmetic unit, power consumption is previously increased by the pre-access instruction.Type: ApplicationFiled: July 22, 2013Publication date: March 20, 2014Applicant: FUJITSU LIMITEDInventor: HIROSHI OKANO
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Publication number: 20140049316Abstract: A semiconductor integrated circuit includes a user circuit and a power supply noise suppression circuit. The user circuit includes a plurality of circuit modules each containing an operation ratio control circuit. The power supply noise suppression circuit judges an amount of current fluctuation occurring in the user circuit by monitoring an operation ratio of each of the plurality of circuit modules, and controls, via each of the operation ratio control circuits, the operation ratio of a corresponding one of the circuit modules in accordance with a result of the judgment of the amount of current fluctuation.Type: ApplicationFiled: October 22, 2013Publication date: February 20, 2014Applicant: FUJITSU LIMITEDInventor: HIROSHI OKANO
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Patent number: 8500886Abstract: Exhaust gas after coal or oil burning has moisture, which hinders carbon dioxide adsorption. It is necessary to completely remove this moisture with the minimum use of energy. The exhaust gas from the burning apparatus is first lowered of its temperature by passing through an total heat exchanger rotor, and the resultant gas which has low temperature and humidity is sent to a carbon dioxide adsorption rotor, thereby removing carbon dioxide from the gas, which is then sent through the total heat exchanger rotor with the resultant desorption of moisture adsorbed there and is exhausted to outside atmosphere, while the carbon dioxide adsorption rotor is desorbed of its carbon dioxide using water vapor, with the resultant very humid carbon dioxide to be sent to a processing system such as for underground burial.Type: GrantFiled: June 20, 2011Date of Patent: August 6, 2013Assignee: Seibu Giken Co, LtdInventors: Hiroshi Okano, Tsutomu Hirose
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Publication number: 20120254595Abstract: Instructions decoded by the instruction decoding part are issued to an arithmetic and logic part, a consumption current value that has been consumed by the arithmetic and logic part with instructions issued during a first predetermined period and a consumption current estimated value for a current that is consumed by the arithmetic and logic part with instructions issuable during a second predetermined period of the decoded instructions are calculated, and issuance of some instructions of the decoded instructions is inhibited in the second predetermined period in a case where a change amount of the consumption current estimated value with respect to the consumption current value exceeds a predetermined limit value.Type: ApplicationFiled: June 12, 2012Publication date: October 4, 2012Applicant: FUJITSU LIMITEDInventors: Wenhao WU, Hiroshi Okano, Yukihito Kawabe
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Publication number: 20120000365Abstract: Exhaust gas after coal or oil burning has moisture, which hinders carbon dioxide adsorption. It is necessary to completely remove this moisture with the minimum use of energy. The exhaust gas from the burning apparatus is first lowered of its temperature by passing through an total heat exchanger rotor, and the resultant gas which has low temperature and humidity is sent to a carbon dioxide adsorption rotor, thereby removing carbon dioxide from the gas, which is then sent through the total heat exchanger rotor with the resultant desorption of moisture adsorbed there and is exhausted to outside atmosphere, while the carbon dioxide adsorption rotor is desorbed of its carbon dioxide using water vapor, with the resultant very humid carbon dioxide to be sent to a processing system such as for underground burial.Type: ApplicationFiled: June 20, 2011Publication date: January 5, 2012Applicant: SEIBU-GIKEN CO., LTDInventors: Hiroshi Okano, Tsutomu Hirose
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Publication number: 20110289955Abstract: A desiccant air conditioner has a high energy efficiency due to the absence of excessive heat loss due to ventilation. In order to meet this requirement, the desiccant air conditioner is equipped with a honeycomb rotor wash-coated with agents having capabilities of absorptions of humidity, carbon dioxide and nitrogen, and this honeycomb rotor is divided into at least an absorption zone and a desorption zone. The air in a room is, after being passed through the absorption zone, fed back to the room, and the air which is passed through the desorption zone is exhausted into outside of the room. In this way, carbon dioxide and nitrogen in a room, the latter quantity being corresponded to that of the consumed oxygen in the room, are exhausted into outside of the room, allowing to exhaust carbon dioxide and at the same time to keep the oxygen density to within an allowed limit without the need of excessive ventilation.Type: ApplicationFiled: May 26, 2011Publication date: December 1, 2011Applicant: SEIBU-GIKEN CO., LTD.Inventor: Hiroshi Okano
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Patent number: 8063692Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.Type: GrantFiled: June 10, 2010Date of Patent: November 22, 2011Assignee: Fujitsu LimitedInventor: Hiroshi Okano
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Patent number: 8063509Abstract: A power supply voltage adjusting apparatus includes a voltage setting part that, according to a characteristic variation of a semiconductor integrated circuit, sets a first power supply voltage of a first power supply domain module among a plurality of modules in the semiconductor integrated circuit, each module respectively having a different power supply voltage; a detecting part that compares phases of a first clock signal flowing through the first power supply domain module and a second clock signal flowing through a second power supply domain module to detect a phase difference; and a voltage adjusting part that adjusts a second power supply voltage supplied to the second power supply domain module to reduce the phase difference detected by the detecting part.Type: GrantFiled: September 16, 2009Date of Patent: November 22, 2011Assignee: Fujitsu LimitedInventor: Hiroshi Okano
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Patent number: 8008967Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.Type: GrantFiled: March 19, 2008Date of Patent: August 30, 2011Assignee: Fujitsu LimitedInventors: Hiroshi Okano, Atsuki Inoue
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Publication number: 20100244942Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.Type: ApplicationFiled: June 10, 2010Publication date: September 30, 2010Applicant: FUJITSU LIMITEDInventor: Hiroshi OKANO
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Patent number: 7753995Abstract: A revolving gas adsorption concentrator uses about 300 degree centigrade of hot desorption air. The revolving gas adsorption concentrator prevents leakage of such hot desorption air. An elastic seal which has elasticity divides a honeycomb shape rotor into a desorption zone and an adsorption zone and touches the honeycomb shape rotor. A heat-resistant seal comprises of material whose heat resistance is higher than elastic seal. The heat-resistant seal has two plates which has a mutually opened spacing to prevent hot gas from going to the elastic seal based on the labyrinth effectiveness. The elastic seal is formed in the outside of desorption zone from heat-resistant seal. The seal of the hot desorption air is almost blocked by heat-resistant seal and the desorption air which leaked slightly can be thoroughly blocked completely by elastic seal.Type: GrantFiled: December 11, 2007Date of Patent: July 13, 2010Assignee: Seibu Giken Co., Ltd.Inventors: Hiroshi Okano, Ken-ichiro Yamada
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Publication number: 20100164286Abstract: A power supply voltage adjusting apparatus includes a voltage setting part that, according to a characteristic variation of a semiconductor integrated circuit, sets a first power supply voltage of a first power supply domain module among a plurality of modules in the semiconductor integrated circuit, each module respectively having a different power supply voltage; a detecting part that compares phases of a first clock signal flowing through the first power supply domain module and a second clock signal flowing through a second power supply domain module to detect a phase difference; and a voltage adjusting part that adjusts a second power supply voltage supplied to the second power supply domain module to reduce the phase difference detected by the detecting part.Type: ApplicationFiled: September 16, 2009Publication date: July 1, 2010Applicant: FUJITSU LIMITEDInventor: Hiroshi OKANO
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Publication number: 20090145301Abstract: A revolving gas adsorption concentrator uses about 300 degree centigrade of hot desorption air. The revolving gas adsorption concentrator prevents leakage of such hot desorption air. An elastic seal which has elasticity divides a honeycomb shape rotor into a desorption zone and an adsorption zone and touches the honeycomb shape rotor. A heat-resistant seal comprises of material whose heat resistance is higher than elastic seal. The heat-resistant seal has two plates which has a mutually opened spacing to prevent hot gas from going to the elastic seal based on the labyrinth effectiveness. The elastic seal is formed in the outside of desorption zone from heat-resistant seal. The seal of the hot desorption air is almost blocked by heat-resistant seal and the desorption air which leaked slightly can be thoroughly blocked completely by elastic seal.Type: ApplicationFiled: December 11, 2007Publication date: June 11, 2009Applicant: SEIBU GIKEN CO., LTD.Inventors: Hiroshi Okano, Ken-ichiro Yamada
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Publication number: 20080191681Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.Type: ApplicationFiled: March 19, 2008Publication date: August 14, 2008Applicant: Fujitsu LimitedInventors: Hiroshi OKANO, Atsuki Inoue
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Patent number: 7221478Abstract: A digital image receiving apparatus includes a media drive (11) for reading image information from a storage medium (M1), an image information processing unit (22) for processing the image information to display a plurality of images in the image information read by the media drive, in thumbnail image form on a display (12), and an order information processing unit (24) for creating order information including which images to be printed from a printing order given by a customer for each image displayed on the display (12). The image information processing unit (22) includes an image data size acquisition unit (22a) for acquiring image data sizes of image data included in the image information and serving as printing sources. Information on the image data sizes acquired is displayed on the display (12) as associated with thumbnail images of corresponding image information.Type: GrantFiled: August 29, 2002Date of Patent: May 22, 2007Assignee: Noritsu Koki Co., Ltd.Inventors: Tetsuya Wada, Hiroshi Okano
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Patent number: 7140001Abstract: A framework for a business application system, which is used for constructing the business application system, is described by an object-oriented language having characteristics of abstraction and inheritance. The framework includes an abstract class group 10 having abstractly defined the structure and behavior of the business application system, and a common component group 20 including a plurality of common components commonly for use in the business application system. The abstract class group 10 includes a system core class group 11 having abstractly defined the basic structure and behavior of the business application system, and a screen system class group 12, a report system class group 13 and a business logic system class group 14, which inherit the system core class group 11.Type: GrantFiled: March 5, 1999Date of Patent: November 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Mari Natori, Hiroshi Okano
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Patent number: 7134004Abstract: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.Type: GrantFiled: September 20, 2000Date of Patent: November 7, 2006Assignee: Fujitsu LimitedInventors: Shin-ichiro Tago, Taizo Sato, Yoshimasa Takebe, Yasuhiro Yamazaki, Teruhiko Kamigata, Atsuhiro Suga, Hiroshi Okano, Hitoshi Yoda
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Patent number: 7133973Abstract: An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous. As a result, the subsequent operations can executed even if the present operation has not been completed.Type: GrantFiled: January 31, 2003Date of Patent: November 7, 2006Assignee: Fujitsu LimitedInventors: Fumihiko Hayakawa, Hiroshi Okano
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Publication number: 20060224870Abstract: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target addreType: ApplicationFiled: May 31, 2006Publication date: October 5, 2006Inventors: Shin-ichiro Tago, Taizo Sato, Yoshimasa Takebe, Yasuhiro Yamazaki, Teruhiko Kamigata, Atsuhiro Suga, Hiroshi Okano, Hitoshi Yoda
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Patent number: 7096375Abstract: A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.Type: GrantFiled: November 19, 2002Date of Patent: August 22, 2006Assignee: Fujitsu LimitedInventors: Shigetoshi Wakayama, Hiroshi Okano, Yoshio Hirose