Abstract: A power storage system includes: a power storage unit including a storage battery, a charging section that charges the storage battery, and a detection section that detects at least one status of the storage battery and the charging section from a plurality of perspectives; and an abnormality detection unit including an input section that acquires transmission information from the power storage unit via a transmission path, the transmission information including a plurality of detected status values, and an abnormality detection section that detects abnormality of the power storage unit by a multivariate analysis performed on the plurality of acquired status values.

Abstract: A power storage system includes: a power storage unit including a storage battery, a charging section that charges the storage battery, and a detection section that detects at least one status of the storage battery and the charging section from a plurality of perspectives; and an abnormality detection unit including an input section that acquires transmission information from the power storage unit via a transmission path, the transmission information including a plurality of detected status values, and an abnormality detection section that detects abnormality of the power storage unit by a multivariate analysis performed on the plurality of acquired status values.

Abstract: A load driving circuit in which a load is connected to the connecting point of transistors as low-side and high-side main switch elements that have a totem pole structure and are connected between a pair of drive voltage supply lines. A protection circuit section is provided for the high-side transistor. In the protection circuit section, a resistor as a voltage control element is provided for a MOSFET as an overvoltage prevention switch and a capacitor is connected between the gate and the drain of the MOSFET.

Abstract: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.

Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.

Abstract: A load driving circuit in which a load is connected to the connecting point of transistors as low-side and high-side main switch elements that have a totem pole structure and are connected between a pair of drive voltage supply lines. A protection circuit section is provided for the high-side transistor. In the protection circuit section, a resistor as a voltage control element is provided for a MOSFET as an overvoltage prevention switch and a capacitor is connected between the gate and the drain of the MOSFET.

Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.

Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals DO thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.

Abstract: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.

Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals Do thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.