Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.

Abstract: A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.

Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: A data transfer controller for transferring display data to N individual (where N is an integer, N?2) display devices is disclosed. The data transfer controller includes a clock signal generating means, and a timing control means. The clock signal generating means generates clock signals. The timing control means adjusts the timing of the vertical synchronization signals included in the display data based on the clock signal for N individual display devices. The timing control means adjusts the timing of the vertical synchronization signals such that no vertical blanking period overlaps any other vertical blanking period, or adjusts the timing of the vertical synchronization signals such that no vertical display period overlaps a vertical display period of another display device among the display data transferred to each display device.

Abstract: A first transmission line for transmitting a first signal and a second transmission line for transmitting a second signal, which has the reverse phase of the first signal, are connected in series with a common mode choke coil. A third transmission line and fourth transmission line are each connected in series with the common mode choke coil, and transmit the first and second signals. A semiconductor device is connected in series with the third and fourth transmission lines, so as to transmit and receive the first and second signals. One end of a first terminator is connected in parallel with the first transmission line, and the other end is connected to the common mode choke coil. One end of a second terminator is connected in parallel with the second transmission line, and the other end is connected to the common mode choke coil. The noise eliminating capability of the common mode choke coil is increased by means of this structure.

Abstract: In a filter circuit (1), a common mode choke (2) and a normal mode choke (3) have extremely high and low impedances, respectively, for common mode signals received through two input terminals (1a and 1b). The chokes have the opposite impedance characteristics for differential signals. In particular, the difference in impedance is large. Furthermore, the normal mode choke (3) is installed as a previous stage of the common mode choke (2). Accordingly, common mode noises which enter the two input terminals (1a and 1b) penetrate the normal mode choke (3), but neither penetrate the common mode choke (2) nor are reflected from the common mode choke (2). In particular, common mode currents flow through the normal mode choke (3) but do not flow through the common mode choke (2).

Abstract: According to LSI packages of the BGA type and the like, the number of source voltage supply terminals on an LSI package needs to be around the same as the number of power supply terminals on an LSI chip, in order to prevent the impact of high-frequency currents generated due to a switching operation in an internal circuit in the LSI chip. According to the present invention, however, at least two power supply terminals on an LSI chip are connected to one source voltage supply terminal on an LSI package. In addition, a capacitor element is embedded in a substrate forming the main body of the LSI package, and the capacitor element is provided between a source voltage supply terminal and an earth terminal.

Abstract: A signal receiver (11) receives an analog signal via a twisted pair cable (31). An A/D converter (12) converts the analog signal to a digital signal. A phase detection unit (14) detects the phase of the digital signal, and generates a reception timing signal. A transmission timing generation unit (15) controls, based on the reception timing signal, timing for a transmission processing unit (16) to output the digital signal such that the reception signal (point A) and a transmission signal (point D) are different in phase by a predetermined degree. The transmission processing unit (16) outputs, in accordance with the timing, a digital signal obtained by performing mapping on data inputted from a connection device (20). A D/A converter (17) converts the digital signal to an analog signal. A signal transmitter (18) transmits the analog signal via a twisted pair cable (32).

Abstract: A data transfer controller for transferring display data to N individual (where N is an integer, N?2) display devices is disclosed. The data transfer controller includes a clock signal generating means, and a timing control means. The clock signal generating means generates clock signals. The timing control means adjusts the timing of the vertical synchronization signals included in the display data based on the clock signal for N individual display devices. The timing control means adjusts the timing of the vertical synchronization signals such that no vertical blanking period overlaps any other vertical blanking period, or adjusts the timing of the vertical synchronization signals such that no vertical display period overlaps a vertical display period of another display device among the display data transferred to each display device.

Abstract: A first transmission line for transmitting a first signal and a second transmission line for transmitting a second signal, which has the reverse phase of the first signal, are connected in series with a common mode choke coil. A third transmission line and fourth transmission line are each connected in series with the common mode choke coil, and transmit the first and second signals. A semiconductor device is connected in series with the third and fourth transmission lines, so as to transmit and receive the first and second signals. One end of a first terminator is connected in parallel with the first transmission line, and the other end is connected to the common mode choke coil. One end of a second terminator is connected in parallel with the second transmission line, and the other end is connected to the common mode choke coil. The noise eliminating capability of the common mode choke coil is increase by means of this structure.

Abstract: According to LSI packages of the BGA type and the like, the number of source voltage supply terminals on an LSI package needs to be around the same as the number of power supply terminals on an LSI chip, in order to prevent the impact of high-frequency currents generated due to a switching operation in an internal circuit in the LSI chip. According to the present invention, however, at least two power supply terminals on an LSI chip are connected to one source voltage supply terminal on an LSI package. In addition, a capacitor element is embedded in a substrate forming the main body of the LSI package, and the capacitor element is provided between a source voltage supply terminal and an earth terminal.

Abstract: A low density body such as a sheet, board or molding usable as a cushioning material, heat-insulating material, sound-absorbing material, filter, low density base paper or the like is provided. The low density body having a density of 0.05 to 0.45 g/cm.sup.3 is prepared by dewatering a slurry containing fine fibers having a bond-reinforcing factor of at least 0.15 and curled fibers having a wet curl factor of 0.4 to 1.0, and drying the resultant product.

Abstract: A freezing apparatus comprises a cooling hollow body to receive food products to be frozen thereon and to be driven for rotation, a flexible container made of a flexible sheet material which is arranged on the upper surface of the cooling hollow body so as to cover said products placed on said upper surface, a cold brine circulating path including the hollow portion of the cooling hollow body and the interior of the flexible container which are mutually communicated to feed cold brine, a plurality of adapters attached to the outer periphery of the flexible container, and a guide rail provided around the outer periphery of the flexible container to slidably support the adapters. The flexible container is moved synchronousely with the cooling hollow body due to a frictional force resulted between the flexible container and the cooling hollow body.

Abstract: A freezing apparatus comprises a cooling hollow body to receive food products to be frozen thereon and to be driven for rotation, a flexible container made of a flexible sheet material which is arranged on the upper surface of the cooling hollow body so as to cover said products placed on said upper surface, a cold brine circulating path including the hollow portion of the cooling hollow body and the interior of the flexible container which are mutually communicated to feed cold brine, a plurality of adapters attached to the outer periphery of the flexible container, and a guide rail provided around the outer periphery of the flexible container to slidably support the adapters. The flexible container is moved synchronously with the cooling hollow body due to a frictional force resulted between the flexible container and the cooling hollow body.