Abstract: A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.

Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.

Abstract: A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The write circuit sets a variable resistance element of another memory cell different from a faulty memory cell and located on at least one of a bit line and a word line that includes the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in a first low resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.

Abstract: The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The write circuit sets a variable resistance element of another memory cell different from a faulty memory cell and located on at least one of a bit line and a word line that includes the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in a first low resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.

Abstract: The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

Abstract: A semiconductor integrated circuit includes: a macro cell having a plurality of circuit elements; a first macro cell power supply line for supplying a first potential to the macro cell; and a second macro cell power supply line formed in a same wiring layer as a wiring layer of the first macro cell power supply line, for supplying a second potential to the macro cell. The first and second macro cell power supply lines are provided on the macro cell. The second macro cell power supply line extends in a first direction that is a longitudinal direction of the first macro cell power supply line.

Abstract: A semiconductor integrated circuit includes: a macro cell having a plurality of circuit elements; a first macro cell power supply line for supplying a first potential to the macro cell; and a second macro cell power supply line formed in a same wiring layer as a wiring layer of the first macro cell power supply line, for supplying a second potential to the macro cell. The first and second macro cell power supply lines are provided on the macro cell. The second macro cell power supply line extends in a first direction that is a longitudinal direction of the first macro cell power supply line.

Abstract: A semiconductor memory device with a high-capacity memory cell array includes a plurality of global word lines per memory cell row of the memory cell array. The global word lines are formed in two wiring layers (upper and lower layers). This substantially reduces the number of memory cells connected per global word line without increasing the memory cell size, allowing for an improved operation speed of the memory cells and reduced power consumption.

Abstract: The semiconductor memory device includes a memory cell array, a block selection circuit, a row decoder, a word driver, and a column decoder. The memory cell array includes a plurality of memory cells, a plurality of main word lines and a plurality of bit line pairs. The plurality of main word lines are provided corresponding to the rows, that is, m main word lines are provided per row (where m is an integer equal to or greater than two). The plurality of bit line pairs are provided corresponding to the columns. The memory cell array is divided into a plurality of memory blocks in the column direction. Each of the plurality of memory blocks further includes a plurality of sub word lines. The plurality of sub word lines are provided corresponding to the rows. Each of the plurality of sub word lines is connected to one of the m main word lines of the corresponding row.

Abstract: A semiconductor memory device with a high-capacity memory cell array includes a plurality of global word lines per memory cell row of the memory cell array. The global word lines are formed in two wiring layers (upper and lower layers). This substantially reduces the number of memory cells connected per global word line without increasing the memory cell size, allowing for an improved operation speed of the memory cells and reduced power consumption.

Abstract: The semiconductor memory device includes a memory cell array, a block selection circuit, a row decoder, a word driver, and a column decoder. The memory cell array includes a plurality of memory cells, a plurality of main word lines and a plurality of bit line pairs. The plurality of main word lines are provided corresponding to the rows, that is, m main word lines are provided per row (where m is an integer equal to or greater than two). The plurality of bit line pairs are provided corresponding to the columns. The memory cell array is divided into a plurality of memory blocks in the column direction. Each of the plurality of memory blocks further includes a plurality of sub word lines. The plurality of sub word lines are provided corresponding to the rows. Each of the plurality of sub word lines is connected to one of the m main word lines of the corresponding row.

Abstract: The semiconductor storage device of this invention includes a memory cell array; word lines; bit lines; a peripheral circuit for controlling the potentials of the word lines and the bit lines; a peripheral circuit power line for connecting a power voltage supply terminal to the peripheral circuit; a peripheral circuit power switch; a memory cell array power line; a constant voltage supply line for connecting the word lines to ground; a word line switch for fixing a voltage disposed on the constant voltage supply line; and the like. The potential of the word lines is fixed by controlling the word line switch to be placed in a conducting state before switching the peripheral circuit power switch. Thus, data in the memory cells can be prevented from being destroyed by a transient current caused in turning on/off the switch.