Patents by Inventor Hiroshi Yanagimoto

Hiroshi Yanagimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133070
    Abstract: A mask structure includes a screen mask having a penetrating portion with a predetermined pattern. The screen mask includes a mesh portion having an opening formed in a grid pattern, and a mask portion having the penetrating portion and being fixed to the mesh portion so as to face the substrate. The mask portion includes a core portion that retains the shape of the mask portion, and a seal portion made of an elastic material softer than the material of the core portion and contacting the substrate.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki KONDOH, Keiji KURODA, Koji INAGAKI, Kazuaki OKAMOTO, Hiroshi YANAGIMOTO
  • Publication number: 20240079103
    Abstract: An information processing device (40) according to one embodiment of the present disclosure includes: an analysis unit (41) being a first data generation unit that generates objective score data, which indicates objective scores in time series, based on a plurality of pieces of objective data regarding a patient; a processing unit (42) being a second data generation unit that generates subjective score data, which indicates subjective scores in time series, based on a plurality of pieces of subjective data obtained from the patient; and a generation unit (44) being an image generation unit that generates a score image indicating the objective score data and the subjective score data.
    Type: Application
    Filed: December 23, 2021
    Publication date: March 7, 2024
    Inventors: RITSUKO KANO, EIJIRO MORI, SHINSUKE NOGUCHI, KAZUMI HIRANO, TAKAFUMI YANAGIMOTO, KOJI SATO, HIROSHI HARA
  • Patent number: 11903141
    Abstract: A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 13, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji Kuroda, Rentaro Mori, Hiroshi Yanagimoto, Haruki Kondoh, Kazuaki Okamoto, Akira Kato
  • Patent number: 11785721
    Abstract: First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: October 10, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki Kondoh, Rentaro Mori, Keiji Kuroda, Kazuaki Okamoto, Akira Kato, Jyunya Murai, Hiroshi Yanagimoto, Kenji Nakamura, Tomoya Okazaki
  • Publication number: 20230302578
    Abstract: Provided is a method for manufacturing a board with a roughened surface and a method for manufacturing a board having a plated layer that allow easily manufacturing the board having a plated layer. One of embodiments is a method for manufacturing a board with a surface roughened for wiring formation. The method for manufacturing a board includes performing laser ablation on a board containing a resin at least on a surface of the board. A laser light irradiated in the laser ablation is a laser light having a pulse width of 1 ps or less, a wavelength of 320 nm or more, and an output of 1 W or less.
    Type: Application
    Filed: January 26, 2023
    Publication date: September 28, 2023
    Inventors: Hiroshi YANAGIMOTO, Oji KUNO, Jyunya MURAI, Keiji KURODA, Tomoya OKAZAKI, Rentaro MORI
  • Patent number: 11700686
    Abstract: A method for manufacturing a wiring board capable of improving adhesion between an underlayer and a seed layer. An electrically conductive underlayer is disposed on the surface of an insulating substrate and a seed layer containing metal is disposed on the surface of the underlayer to prepare a substrate with seed-layer. A diffusion layer in which elements forming the underlayer and seed layer are mutually diffused is formed between the underlayer and the seed layer, by irradiating the seed layer with a laser beam. A metal layer is formed on the surface of the seed layer by disposing a solid electrolyte membrane between an anode and the seed layer as a cathode and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from the insulating substrate.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: July 11, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji Kuroda, Haruki Kondoh, Kazuaki Okamoto, Rentaro Mori, Hiroshi Yanagimoto
  • Patent number: 11696410
    Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: July 4, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki Kondoh, Rentaro Mori, Hiroshi Yanagimoto, Keiji Kuroda, Kazuaki Okamoto
  • Patent number: 11665829
    Abstract: A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 30, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki Kondoh, Rentaro Mori, Keiji Kuroda, Hiroshi Yanagimoto, Kazuaki Okamoto
  • Patent number: 11490528
    Abstract: Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 1, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kazuaki Okamoto, Hiroshi Yanagimoto, Rentaro Mori
  • Publication number: 20220304162
    Abstract: Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 22, 2022
    Inventors: Kazuaki OKAMOTO, Hiroshi YANAGIMOTO, Rentaro MORI
  • Publication number: 20220272847
    Abstract: First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 25, 2022
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki KONDOH, Rentaro MORI, Keiji KURODA, Kazuaki OKAMOTO, Akira KATO, Jyunya MURAI, Hiroshi YANAGIMOTO, Kenji NAKAMURA, Tomoya OKAZAKI
  • Patent number: 11425823
    Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate including an insulation substrate, a conductive undercoat layer, and a conductive seed layer provided in a first region, in that order, is first prepared. An insulation layer covering the seed layer and the undercoat layer is then formed. Subsequently, the insulation layer is etched to expose a surface of the seed layer and form a remaining insulation layer covering the undercoat layer in the second region. Subsequently, a voltage is applied between an anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing aqueous solution disposed between the seed layer and the anode and the membrane and the seed layer pressed into contact with each other, thereby a metal layer being formed on the surface of the seed layer. Thereafter, the remaining insulation layer is removed and the undercoat layer is etched.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 23, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki Kondoh, Rentaro Mori, Hiroshi Yanagimoto, Keiji Kuroda, Kazuaki Okamoto
  • Patent number: 11425824
    Abstract: A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 23, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji Kuroda, Haruki Kondoh, Kazuaki Okamoto, Rentaro Mori, Hiroshi Yanagimoto
  • Publication number: 20220061165
    Abstract: A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 24, 2022
    Inventors: Keiji KURODA, Rentaro MORI, Hiroshi YANAGIMOTO, Haruki KONDOH, Kazuaki OKAMOTO, Akira KATO
  • Publication number: 20220007506
    Abstract: A method for manufacturing a wiring board capable of improving adhesion between an underlayer and a seed layer. An electrically conductive underlayer is disposed on the surface of an insulating substrate and a seed layer containing metal is disposed on the surface of the underlayer to prepare a substrate with seed-layer. A diffusion layer in which elements forming the underlayer and seed layer are mutually diffused is formed between the underlayer and the seed layer, by irradiating the seed layer with a laser beam. A metal layer is formed on the surface of the seed layer by disposing a solid electrolyte membrane between an anode and the seed layer as a cathode and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from the insulating substrate.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 6, 2022
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji KURODA, Haruki KONDOH, Kazuaki OKAMOTO, Rentaro MORI, Hiroshi YANAGIMOTO
  • Publication number: 20210410291
    Abstract: A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 30, 2021
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji KURODA, Haruki KONDOH, Kazuaki OKAMOTO, Rentaro MORI, Hiroshi YANAGIMOTO
  • Publication number: 20210392753
    Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate including an insulation substrate, a conductive undercoat layer, and a conductive seed layer provided in a first region, in that order, is first prepared. An insulation layer covering the seed layer and the undercoat layer is then formed. Subsequently, the insulation layer is etched to expose a surface of the seed layer and form a remaining insulation layer covering the undercoat layer in the second region. Subsequently, a voltage is applied between an anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing aqueous solution disposed between the seed layer and the anode and the membrane and the seed layer pressed into contact with each other, thereby a metal layer being formed on the surface of the seed layer. Thereafter, the remaining insulation layer is removed and the undercoat layer is etched.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 16, 2021
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki KONDOH, Rentaro MORI, Hiroshi YANAGIMOTO, Keiji KURODA, Kazuaki OKAMOTO
  • Publication number: 20210378103
    Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.
    Type: Application
    Filed: May 19, 2021
    Publication date: December 2, 2021
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki KONDOH, Rentaro MORI, Hiroshi YANAGIMOTO, Keiji KURODA, Kazuaki OKAMOTO
  • Publication number: 20210204409
    Abstract: A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.
    Type: Application
    Filed: December 15, 2020
    Publication date: July 1, 2021
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Haruki KONDOH, Rentaro MORI, Keiji KURODA, Hiroshi YANAGIMOTO, Kazuaki OKAMOTO
  • Publication number: 20210084774
    Abstract: Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 18, 2021
    Inventors: Kazuaki OKAMOTO, Hiroshi YANAGIMOTO, Rentaro MORI