Patents by Inventor Hiroshi Yao
Hiroshi Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10289480Abstract: A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip. The controller controls the memory. Each of the first and second memory chips includes string units and blocks including the string units. The memory holds information indicating a partial bad block including a bad string unit, and indicating which one of string units is the bad string unit in the partial bad block.Type: GrantFiled: September 8, 2015Date of Patent: May 14, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Naomi Takeda, Tokumasa Hara, Masanobu Shirakawa, Hiroshi Yao
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Patent number: 10277258Abstract: According to one embodiment, in a case where a first command is received from a host, a storage device starts a first process. The storage device transmits a first response to the host in a case where a first condition is satisfied and transmits a second response and an interrupt signal to the host in a case where the first process is completed. The host, in a case where the first response is received, stops the polling and receives the second response based on reception of the interrupt signal.Type: GrantFiled: March 16, 2017Date of Patent: April 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takayuki Akamine, Kenichiro Yoshii, Hiroshi Yao
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Publication number: 20190087324Abstract: According to one embodiment, a memory system includes a non-volatile first memory, and a controller. The controller associates a first number of consecutive logical addresses with the first number of physical addresses which are included in a second number of consecutive physical addresses of the first memory. The controller executes a first updating and a second updating. The first updating includes associating a first physical address among the second number of physical addresses with a first logical address.Type: ApplicationFiled: March 7, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Naomi TAKEDA, Kenta Yasufuku, Hiroshi Yao
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Patent number: 10157141Abstract: According to one embodiment, when the first command is received from a host, a controller translates a first address designated by a first command into a second address representing a real address of the nonvolatile memory based on a first mapping and accesses the translated second address of the nonvolatile memory. The controller determines whether or not the first mapping is changed based on a degree of wear of the nonvolatile memory and changes some of all the correspondence relations in a case where the first mapping is changed.Type: GrantFiled: September 1, 2016Date of Patent: December 18, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kenichiro Yoshii, Hiroshi Yao
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Publication number: 20180356984Abstract: According to one embodiment, a memory system comprises a non-volatile semiconductor memory having a plurality of first storage areas, the first storage areas being capable of including one or more second storage areas, a plurality of third storage areas in which data is written in a first mode, and a plurality of fourth storage areas in which data is written in a second mode, the first mode being different from the second mode, and processing circuitry.Type: ApplicationFiled: July 24, 2018Publication date: December 13, 2018Applicant: Toshiba Memory CorporationInventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI
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Publication number: 20180277204Abstract: A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. The first voltage is different from the second voltage. The first read data has a first value or a second value with the first value being different from the second value. The second read data has the first value or the second value.Type: ApplicationFiled: September 13, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventors: Marie TAKADA, Masanobu SHIRAKAWA, Hiroshi YAO
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Patent number: 10061377Abstract: According to one embodiment, when shifting to a sleep mode, a processor of a memory device transmits a first command and saving data to a host and issues a power shut-off request. The first command is a command for writing data to a first memory of the host. The saving data includes register information. The register information includes register data stored in the control register and an address of the control register. A power supply circuit shuts off power supply to a second memory of the memory device, the control register, the processor, and a peripheral circuit in response to the issued power shut-off request.Type: GrantFiled: September 1, 2015Date of Patent: August 28, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Daisuke Iwai, Hiroshi Yao
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Patent number: 10055132Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.Type: GrantFiled: January 25, 2018Date of Patent: August 21, 2018Assignee: Toshiba Memory CorporationInventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
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Patent number: 10019158Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to maintain a relationship between a first parameter value and a second parameter value for each of some pages of the non-volatile memory, determine a first parameter value to be used for reading data from a target page of the non-volatile memory based on a first parameter value of a first page and a first parameter value of a second page, when the relationship is maintained for each of the first and second pages and is not maintained for the target page, and carry out a read operation with respect to the target page using the determined first parameter value.Type: GrantFiled: February 28, 2017Date of Patent: July 10, 2018Assignee: Toshiba Memory CorporationInventors: Daiki Watanabe, Hiroshi Yao
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Publication number: 20180188963Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.Type: ApplicationFiled: January 25, 2018Publication date: July 5, 2018Applicant: Toshiba Memory CorporationInventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
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Patent number: 9966146Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.Type: GrantFiled: March 3, 2015Date of Patent: May 8, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Daiki Watanabe, Hiroshi Sukegawa, Hiroshi Yao, Tokumasa Hara, Naomi Takeda
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Publication number: 20180076833Abstract: According to one embodiment, in a case where a first command is received from a host, a storage device starts a first process. The storage device transmits a first response to the host in a case where a first condition is satisfied and transmits a second response and an interrupt signal to the host in a case where the first process is completed. The host, in a case where the first response is received, stops the polling and receives the second response based on reception of the interrupt signal.Type: ApplicationFiled: March 16, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takayuki AKAMINE, Kenichiro YOSHll, Hiroshi YAO
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Patent number: 9910597Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.Type: GrantFiled: December 27, 2016Date of Patent: March 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
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Patent number: 9891848Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.Type: GrantFiled: September 8, 2015Date of Patent: February 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii
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Publication number: 20180039523Abstract: An information processing system includes a first core, a second core having a processing speed that is slower than the first core, a first memory, a second memory having a slower response time than the first memory, and a management processor. The management processor is configured to determine a core for executing a task, cause program data for executing the task to be copied to the first memory and then cause the first core to execute the task using the program data in the first memory, when the first core is determined as the core for executing the task, and cause the program data for executing the task to be copied to the second memory and then cause the second core to execute the task using the program data in the second memory, when the second core is determined as the core for executing the task.Type: ApplicationFiled: February 21, 2017Publication date: February 8, 2018Inventors: Takayuki AKAMINE, Kenichiro YOSHII, Hiroshi YAO
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Patent number: 9799406Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.Type: GrantFiled: September 2, 2015Date of Patent: October 24, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Manabu Sato, Daiki Watanabe, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Naomi Takeda, Noboru Shibata, Takahiro Shimizu
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Publication number: 20170271022Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to maintain a relationship between a first parameter value and a second parameter value for each of some pages of the non-volatile memory, determine a first parameter value to be used for reading data from a target page of the non-volatile memory based on a first parameter value of a first page and a first parameter value of a second page, when the relationship is maintained for each of the first and second pages and is not maintained for the target page, and carry out a read operation with respect to the target page using the determined first parameter value.Type: ApplicationFiled: February 28, 2017Publication date: September 21, 2017Inventors: Daiki WATANABE, Hiroshi YAO
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Publication number: 20170262377Abstract: According to one embodiment, when the first command is received from a host, a controller translates a first address designated by a first command into a second address representing a real address of the nonvolatile memory based on a first mapping and accesses the translated second address of the nonvolatile memory. The controller determines whether or not the first mapping is changed based on a degree of wear of the nonvolatile memory and changes some of all the correspondence relations in a case where the first mapping is changed.Type: ApplicationFiled: September 1, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kenichiro Yoshii, Hiroshi Yao
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Patent number: 9720772Abstract: A memory system according to an embodiment includes a plurality of magnetic nanowires, a read unit that reads data from the magnetic nanowires, a shift control unit that shifts domain walls in the magnetic nanowires, and a read control unit. The read control unit is configured to control the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, and when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, determines a misalignment in the data and correct the data based on the misalignment.Type: GrantFiled: July 10, 2015Date of Patent: August 1, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Sukegawa, Hiroshi Yao, Kohsuke Harada
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Publication number: 20170109050Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.Type: ApplicationFiled: December 27, 2016Publication date: April 20, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI