Patents by Inventor Hiroshi Yoshimura

Hiroshi Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162284
    Abstract: A manufacturing method of a semiconductor device including a buffer region in a semiconductor substrate is provided, comprising: obtaining a substrate concentration index related to at least one of an oxygen chemical concentration or a carbon chemical concentration included in the semiconductor substrate; classifying the substrate concentration index as any index range among a predetermined plurality of index ranges; determining an acceleration energy of hydrogen ions to be implanted into the semiconductor substrate to an acceleration energy that is preset to correspond to the classified index range; and forming a buffer region of the semiconductor device by implanting hydrogen ions into the semiconductor substrate with the determined acceleration energy.
    Type: Application
    Filed: September 21, 2023
    Publication date: May 16, 2024
    Inventors: Hiroshi TAKISHITA, Yuusuke OOSHIMA, Takashi YOSHIMURA, Shuntaro YAGUCHI
  • Patent number: 11984482
    Abstract: Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: May 14, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasunori Agata, Takashi Yoshimura, Hiroshi Takishita
  • Publication number: 20240153829
    Abstract: Provided is a method for manufacturing a semiconductor device, wherein the method: obtains correlated information indicating relationship between a process condition under which a doping region is formed and a defect evaluation value of the doping region; forms the doping region in a substrate for evaluation under a set first process condition; obtains a measurement value of the defect evaluation value of the substrate for evaluation in which the doping region has been formed; obtains, in the correlated information, the defect evaluation value corresponding to the first process condition as a reference value, and compares the measurement value of the defect evaluation value with the reference value; and adjusts the process condition in a process of manufacturing the semiconductor device by using the substrate for manufacture.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 9, 2024
    Inventors: Yuusuke OOSHIMA, Takashi YOSHIMURA, Hiroshi TAKISHITA, Shuntaro YAGUCHI
  • Patent number: 11972950
    Abstract: There is provided a semiconductor device, a hydrogen concentration distribution has a hydrogen concentration peak, a helium concentration distribution has a helium concentration peak, and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak; the hydrogen concentration peak and the first donor concentration peak are located at a first depth, and the helium concentration peak and the second donor concentration peak are located at a second depth; each concentration peak has an upward slope; and a value which is obtained by normalizing a gradient of the upward slope of the second donor concentration peak by a gradient of the upward slope of the helium concentration peak is smaller than a value which is obtained by normalizing a gradient of the upward slope of the first donor concentration peak by a gradient of the upward slope of the hydrogen concentration peak.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Meguro, Takashi Yoshimura, Hiroshi Takishita, Naoko Kodama, Yasunori Agata
  • Publication number: 20240101786
    Abstract: To provide an inorganic filler fluidity modifier for improving the fluidity of an inorganic filler.
    Type: Application
    Filed: February 17, 2022
    Publication date: March 28, 2024
    Applicant: DIC Corporation
    Inventors: Hiroshi Yoshimura, Junko Yamamoto, Yusuke Tajiri
  • Patent number: 11935945
    Abstract: Provided is a semiconductor device, comprising: a semiconductor substrate having an upper surface, a lower surface, and a center position equidistant from the upper surface and the lower surface in a depth direction of the semiconductor substrate. An N-type region with an N-type conductivity is provided in the semiconductor substrate such that the N-type region includes the center position of the semiconductor substrate. The N-type region includes an acceptor with a concentration that is a lower concentration than a carrier concentration, and is 0.001 times or more of a carrier concentration at the center position of the semiconductor substrate.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: March 19, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Misaki Meguro, Michio Nemoto
  • Patent number: 11901223
    Abstract: In general, according to one embodiment, a stress analysis method comprising: dividing a surface of an object into a plurality of first rectangles each having a first size, on data; and acquiring a first type value for each of the first rectangles. The method further includes: specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and generating a stress model for a set of the second rectangles by using the second rectangles as an element.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Hiroshi Yoshimura, Kazuyuki Hino, Jiro Higuchi, Sachiyo Ito, Ken Furubayashi
  • Patent number: 11872526
    Abstract: An electrochemical hydrogen compression system includes a hydrogen gas compression part that compresses hydrogen by applying a current between an anode and a cathode provided on two surfaces of a proton exchange film, and a supply pipeline that guides hydrogen discharged from a hydrogen supply source to the hydrogen gas compression part. The hydrogen gas compression part has an outlet for discharging unreacted hydrogen. The electrochemical hydrogen compression system further includes a film resistance meter and a voltmeter that acquire information related to a wet state of the proton exchange film, a fourth opening/closing part and a fifth opening/closing part that regulate discharge of hydrogen from the outlet, and a control device that controls the fourth opening/closing part and the fifth opening/closing part. The control device controls the fourth opening/closing part and the fifth opening/closing part based on at least the wet state of the proton exchange film.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 16, 2024
    Assignee: Honda Motor Co., Ltd.
    Inventors: Hayato Daimon, Hiroshi Yoshimura, Naoki Mitsuta, Shuichiro Kojima
  • Publication number: 20230133719
    Abstract: To provide an inorganic filler dispersion stabilizer capable of reducing the viscosity of a composition containing an inorganic filler and improving the storage stability of the composition containing an inorganic filler. An inorganic filler dispersion stabilizer which is a polyester having carboxyl groups at both terminals.
    Type: Application
    Filed: March 4, 2021
    Publication date: May 4, 2023
    Applicant: DIC Corporation
    Inventors: Junko Yamamoto, Hiroshi Yoshimura, Yusuke Tajiri
  • Patent number: 11462434
    Abstract: A tape mounter includes at least two storage units storing respective tape sets therein, a reader for reading information of the tape sets stored in the respective storage units from RFIDs attached to tubes around which the tape sets are wound as tape rolls, the storage units having shafts inserted in the tubes and being disposed such that they are spaced from the reader by respective different distances, a time measuring unit for measuring reading times spent until the reader receives radio waves generated and transmitted by the RFIDs and reads the information of the tape sets represented by the radio waves, a mapping table containing positions of the storage units corresponding to the respective reading times, and a recognizing section for checking the reading times against the mapping table, and recognizing the positions of the storage units and types of the tape sets.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: October 4, 2022
    Assignee: DISCO CORPORATION
    Inventor: Hiroshi Yoshimura
  • Publication number: 20220298656
    Abstract: An electrochemical hydrogen compressor comprises a unit cell that includes: an electrolyte membrane having hydrogen ion conductivity; an anode current collector stacked on one main surface side of the electrolyte membrane, a support member (for example, a flow field member or an anode separator) arranged so as to face the anode current collector; and a cathode current collector stacked on another main surface side of the electrolyte membrane, wherein the anode current collector is formed of a hydrophilic conductive material having a plurality of vent holes and has a surface facing the support member, the surface being subjected to a water-repellent treatment.
    Type: Application
    Filed: February 10, 2022
    Publication date: September 22, 2022
    Inventors: Shoji TAKASUGI, Hiroshi YOSHIMURA
  • Publication number: 20220185665
    Abstract: An electrochemical hydrogen compression system includes a hydrogen gas compression part that compresses hydrogen by applying a current between an anode and a cathode provided on two surfaces of a proton exchange film, and a supply pipeline that guides hydrogen discharged from a hydrogen supply source to the hydrogen gas compression part. The hydrogen gas compression part has an outlet for discharging unreacted hydrogen. The electrochemical hydrogen compression system further includes a film resistance meter and a voltmeter that acquire information related to a wet state of the proton exchange film, a fourth opening/closing part and a fifth opening/closing part that regulate discharge of hydrogen from the outlet, and a control device that controls the fourth opening/closing part and the fifth opening/closing part. The control device controls the fourth opening/closing part and the fifth opening/closing part based on at least the wet state of the proton exchange film.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Applicant: Honda Motor Co., Ltd.
    Inventors: Hayato DAIMON, Hiroshi YOSHIMURA, Naoki MITSUTA, Shuichiro KOJIMA
  • Publication number: 20220041858
    Abstract: A fluidity modifier for a coating material or the like contains an ester resin represented by the following general formula (I) or general formula (II) (Y represents a hydrogen atom or a monocarboxylic acid residue having 1 to 9 carbon atoms, G represents an aliphatic diol residue having 2 to 9 carbon atoms, A represents an aliphatic dicarboxylic acid residue having 2 to 10 carbon atoms, X represents a dicarboxylic acid residue having 1 to 8 carbon atoms, Z represents a monoalcohol residue having 2 to 10 carbon atoms, n represents the number of repeating units and is an integer of 0 to 30, and m represents the number of repeating units and is an integer of 0 to 30; G and A may be the same or different for each repeating unit, and a plurality of G may be the same as or different from each other).
    Type: Application
    Filed: September 12, 2019
    Publication date: February 10, 2022
    Applicant: DIC Corporation
    Inventors: Daiki Noro, Hiroshi Yoshimura, Junko Yamamoto, Yusuke Tajiri
  • Publication number: 20210296166
    Abstract: In general, according to one embodiment, a stress analysis method comprising: dividing a surface of an object into a plurality of first rectangles each having a first size, on data; and acquiring a first type value for each of the first rectangles. The method further includes: specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and generating a stress model for a set of the second rectangles by using the second rectangles as an element.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Hiroshi YOSHIMURA, Kazuyuki HINO, Jiro HIGUCHI, Sachiyo ITO, Ken FURUBAYASHI
  • Patent number: 10982123
    Abstract: Provided is a sealing material for multi-layered glasses, including: a polysulfide resin (A) and a polyester resin (B) which is represented by Formula (1-1): or Formula (1-2): wherein A represents a dibasic acid residue, G represents a diol residue, X1 and X2 represent a hydrogen atom or a group represented by Formula (2-1): wherein R represents an aromatic group or an aliphatic group, and X3 and X4 represent an aromatic group or an aliphatic group, n and m each represent the average number of repetitions of a repeating unit in parentheses and are each a numerical value larger than 0, and some or all A's are aromatic dibasic acid residues, and which has an aromatic dibasic acid residue content of 20 to 70% based on chemical formula weights calculated from the chemical formulae represented by [ ]N and [ ]M and also has a number average molecular weight of 400 to 5,000.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 20, 2021
    Assignee: DIC Corporation
    Inventors: Daiki Noro, Hiroshi Yoshimura, Yusuke Tajiri
  • Publication number: 20210111061
    Abstract: A tape mounter includes at least two storage units storing respective tape sets therein, a reader for reading information of the tape sets stored in the respective storage units from RFIDs attached to tubes around which the tape sets are wound as tape rolls, the storage units having shafts inserted in the tubes and being disposed such that they are spaced from the reader by respective different distances, a time measuring unit for measuring reading times spent until the reader receives radio waves generated and transmitted by the RFIDs and reads the information of the tape sets represented by the radio waves, a mapping table containing positions of the storage units corresponding to the respective reading times, and a recognizing section for checking the reading times against the mapping table, and recognizing the positions of the storage units and types of the tape sets.
    Type: Application
    Filed: October 2, 2020
    Publication date: April 15, 2021
    Inventor: Hiroshi YOSHIMURA
  • Patent number: 10943811
    Abstract: A tape affixing apparatus includes: a holding unit including a frame holding unit and a wafer holding portion; a feeding unit configured to feed a tape unit; a winding unit configured to wind a sheet from which a dicing tape is peeled off; a plate configured to be brought into contact with the sheet and peel the tape off from the sheet by bending the tape unit with the sheet on the inside; an affixing roller configured to affix the peeled-off tape to a frame and a wafer; and a nozzle configured to blow air so as to make the peeled-off tape conform to the affixing roller.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 9, 2021
    Assignee: DISCO CORPORATION
    Inventors: Masahiro Wada, Hiroshi Yoshimura, Toshiyasu Rikiishi
  • Patent number: 10892273
    Abstract: A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Sachiyo Ito, Ken Furubayashi, Hiroshi Yoshimura
  • Patent number: 10852648
    Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyuki Hino, Hiromitsu Mashita, Masahiro Miyairi, Hiroshi Yoshimura, Taiga Uno, Sachiyo Ito, Shinichirou Ooki, Kenji Shiraishi, Hirotaka Ichikawa, Yuto Takeuchi
  • Publication number: 20200251484
    Abstract: A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.
    Type: Application
    Filed: June 28, 2019
    Publication date: August 6, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Sachiyo ITO, Ken FURUBAYASHI, Hiroshi YOSHIMURA