Patents by Inventor Hirosi Kato

Hirosi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5986326
    Abstract: A semiconductor device with a bipolar transistor that decreases the parasitic capacitance between a base connection layer and a collector region is provided. This device is comprised of a semiconductor substrate having a main surface, a collector region formed in the substrate, a base region formed in the substrate, an emitter region formed in the substrate, a first dielectric layer formed on the main surface of the substrate to be overlapped with the collector region, a conductive layer formed on the first dielectric layer and applied with a specific electric potential, a second dielectric layer formed to cover the conductive layer, a base connection layer formed on the second dielectric layer and electrically connected to the base region, and a base electrode electrically connected to the base connection layer. The emitter region, the base region, and the collector region constitute a bipolar transistor.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: November 16, 1999
    Assignee: NEC Corporation
    Inventor: Hirosi Kato
  • Patent number: 5736460
    Abstract: In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25 times as large as width of the gold interconnections. In addition, the average dimension of the gold grains is determined so that the mean time to failure is not less than a predetermined period of time.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: April 7, 1998
    Assignee: NEC Corporation
    Inventor: Hirosi Kato
  • Patent number: 5648280
    Abstract: A base region structure involved in a bipolar transistor, wherein the base region comprises a compound semiconductor epitaxial layer formed in a recessed portion provided by etching in an upper region of the semiconductor substrate and the recessed portion has a depth corresponding to a thickness of the compound semiconductor epitaxial layer so that the base region has a top surface positioned at the same level as a top surface of the semiconductor substrate.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: July 15, 1997
    Assignee: NEC Corporation
    Inventor: Hirosi Kato
  • Patent number: 5475265
    Abstract: In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25 times as large as width of the gold interconnections.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: December 12, 1995
    Assignee: NEC Corporation
    Inventor: Hirosi Kato
  • Patent number: 4221686
    Abstract: An ultraviolet radiation polymerizable unsaturated compound containing a polymerizable unsaturated group which is obtained by reacting a reaction product (I) prepared by the reaction between a higher fatty acid having 8 or more carbon atoms or an unsaturated monobasic acid, or a mixture of the two, and a polyisocyanate compound containing at least two isocyanate groups in the molecule, with a reaction product (II) prepared by the reaction between an unsaturated monobasic acid or a higher fatty acid having 8 or more carbon atoms, or a mixture of the two, and an epoxy compound containing at least two epoxy groups in the molecule.
    Type: Grant
    Filed: January 16, 1976
    Date of Patent: September 9, 1980
    Assignees: Sumitomo Chemical Company, Limited, Sakata Shokai Ltd.
    Inventors: Kazuo Sakiyama, Hiroshi Ota, Hirosi Kato
  • Patent number: 4051078
    Abstract: The invention provides a curable composition of polychloroprene, chlorinated polyethylene or polyepichlorohydrin containing at least one metal oxide having an oxidation state of 2 to 5 valences as a curing agent and at least one accelerator of the formulaA--(S).sub.n --A'wherein S is a sulfur atom, A and A' are polyhydroxy aryl groups having 6 to 18 ring carbon atoms and n is zero or an integer of 1 to 4. The accelerators enable a satisfactory rate and state of cure with the metal oxide.
    Type: Grant
    Filed: October 14, 1975
    Date of Patent: September 27, 1977
    Assignee: Dainichi-Nippon Cables, Ltd.
    Inventors: Hirosi Kato, Hideo Fujita
  • Patent number: 3956420
    Abstract: A polyolefin composition comprising polyolefin, a small amount of a ferrocene compound, and an 8-substituted quioline compound has excellent electrical breakdown strength, and therefore is suitable for electrical insulation.A polyolefin composition which is constructed by adding a small amount of a siloxane oligomer to the above polyolefin composition shows more improved electrical breakdown strength and also exhibits superior voltage endurance over a long period of immersion in water.
    Type: Grant
    Filed: September 3, 1974
    Date of Patent: May 11, 1976
    Assignee: Dainichi-Nippon Cables, Ltd.
    Inventors: Hirosi Kato, Nobuyuki Maekawa