Patents by Inventor Hirotada Kuriyama
Hirotada Kuriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7321152Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: August 4, 2006Date of Patent: January 22, 2008Assignee: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 7187040Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: March 14, 2005Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20060267012Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: ApplicationFiled: August 4, 2006Publication date: November 30, 2006Applicant: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 7112854Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: May 2, 1997Date of Patent: September 26, 2006Assignee: Renesas Technology CorporationInventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20050167673Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: ApplicationFiled: March 14, 2005Publication date: August 4, 2005Applicant: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 6882006Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.Type: GrantFiled: July 3, 2002Date of Patent: April 19, 2005Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama, Shigeto Maegawa
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Patent number: 6703953Abstract: A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.Type: GrantFiled: December 10, 1999Date of Patent: March 9, 2004Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Takashi Ipposhi, Hirotada Kuriyama, Hiroki Honda
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Patent number: 6657885Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.Type: GrantFiled: January 28, 2002Date of Patent: December 2, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirotada Kuriyama, Shigenobu Maeda
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Publication number: 20030160715Abstract: A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.Type: ApplicationFiled: December 10, 1999Publication date: August 28, 2003Inventors: Shigenobu Maeda, Takashi Ipposhi, Hirotada Kuriyama, Hiroki Honda
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Patent number: 6563165Abstract: A non-volatile semiconductor memory device comprising: a semiconductor substrate, memory cells, a region of memory cell array in which said memory cells are arranged in a matrix-like form, a region of peripheral circuit, a connecting region for connecting said region of memory cell array to said region of peripheral circuit, and conductive layers provided closest to said substrate with intervals between each other, wherein said intervals of said conductive layers are substantially equal to each other in said region of memory cell array and said connecting region, whereby when insulating films are formed and planarized after forming said conductive layers, it is possible to restrict producing of seams in the insulating films at stripped portions of the conductive layers.Type: GrantFiled: November 25, 1998Date of Patent: May 13, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kiyohiko Sakakibara, Hirotada Kuriyama
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Patent number: 6501178Abstract: In a semiconductor device, a first conductive layer (2) is located on a semiconductor substrate (14) through an insulating film (13a) and beneath a first insulating layer (13f). On the first insulating layer (13f) is formed a second conductive layer (8) followed by a second insulating layer (13g), either or both of which are very thin. A third conductive layer (6) is placed on the second insulating layer (13g). A connecting column (16) extends from the third conducting layer (6) through and forming an end contact with the second conductive layer (8) to the first conducting layer (2) and the substrate (14), with a greater portion of the column resting upon the substrate (14). The third conductive layer (6) forms the gate electrode (6b) of a top gate type TFT.Type: GrantFiled: February 4, 1997Date of Patent: December 31, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirotada Kuriyama, Kazuhito Tsutsumi
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Publication number: 20020195652Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.Type: ApplicationFiled: July 3, 2002Publication date: December 26, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama, Shigeto Maegawa
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Patent number: 6441448Abstract: A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.Type: GrantFiled: April 12, 1999Date of Patent: August 27, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama
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Patent number: 6420751Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.Type: GrantFiled: August 18, 2000Date of Patent: July 16, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama, Shigeto Maegawa
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Publication number: 20020067636Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.Type: ApplicationFiled: January 28, 2002Publication date: June 6, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hirotada Kuriyama, Shigenobu Maeda
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Patent number: 6383860Abstract: A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.Type: GrantFiled: July 20, 2001Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Yasuo Inoue, Hirotada Kuriyama, Shigeto Maegawa, Kyozo Kanamoto, Toshiaki Iwamatsu
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Publication number: 20020043692Abstract: A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.Type: ApplicationFiled: April 12, 1999Publication date: April 18, 2002Inventors: SHIGENOBU MAEDA, YASUO YAMAGUCHI, HIROTADA KURIYAMA
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Patent number: 6359804Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.Type: GrantFiled: October 6, 1998Date of Patent: March 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirotada Kuriyama, Shigenobu Maeda
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Publication number: 20020003241Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.Type: ApplicationFiled: October 6, 1998Publication date: January 10, 2002Inventors: HIROTADA KURIYAMA, SHIGENOBU MAEDA
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Publication number: 20020000603Abstract: A non-volatile semiconductor memory device comprising: a semiconductor substrate, memory cells, a region of memory cell array in which said memory cells are arranged in a matrix-like form, a region of peripheral circuit, a connecting region for connecting said region of memory cell array to said region of peripheral circuit, and conductive layers provided closest to said substrate with intervals between each other, wherein said intervals of said conductive layers are substantially equal to each other in said region of memory cell array and said connecting region, whereby when insulating films are formed and planarized after forming said conductive layers, it is possible to restrict producing of seams in the insulating films at stripped portions of the conductive layers.Type: ApplicationFiled: November 25, 1998Publication date: January 3, 2002Inventors: KIYOHIKO SAKAKIBARA, HIROTADA KURIYAMA