Patents by Inventor Hirotaka Amakawa

Hirotaka Amakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7180114
    Abstract: A semiconductor device includes a silicon substrate having a film thickness smaller than a maximum range of a particle generated by a nuclear reaction between a fast neutron and a silicon atom, and a semiconductor element formed on a surface of the silicon substrate.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: February 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsutoshi Nakamura, Hirotaka Amakawa
  • Patent number: 7162400
    Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: January 9, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sanae Ito, Hirotaka Amakawa
  • Patent number: 7081633
    Abstract: An ion implantation simulator that computes an ion density distribution at high speed and with high accuracy based on a beam dispersion phenomenon in an ion implantation process. The ion implantation simulator is provided with the beam dispersion approximate function storage section 121, which stores a beam dispersion approximate function that is obtained through approximation of ion beam dispersion by using a predetermined function; a beam intensity computing section 131, which computes an area surface beam intensity that indicates an intensity of the ion beam on a surface of an implanted area by using the beam dispersion approximate function; and an ion density distribution computing section 132, which computes the density distribution of the ion, which is implanted by the ion beam into the device through the surface of the implanted area, by using the area surface beam intensity.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: July 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirotaka Amakawa
  • Publication number: 20060102965
    Abstract: There is provided a semiconductor device which includes a projecting semiconductor layer provided on a substrate and having a first side surface and a second side surface opposed to the first side surface, a first gate insulating film provided on the semiconductor layer, a first gate electrode provided on the first gate insulating film, a first and a second diffusion layers provided on respective sides of the first gate electrode and in the semiconductor layer, a first insulating film provided on the first side surface, and a first conductive layer electrically connected to the first gate electrode and provided below the first and second diffusion layers and on a side surface of the first insulating film.
    Type: Application
    Filed: March 18, 2005
    Publication date: May 18, 2006
    Inventors: Sanae Ito, Masaki Kondo, Hirotaka Amakawa
  • Patent number: 6980942
    Abstract: Plural boundary points are generated on a string on the surface of a material and a first length of a line segment between the boundary points is obtained. Then, the displacement of the boundary point according to a process model and the boundary point is moved by the displacement. A second length of the line segment between the boundary points after the boundary point is moved is found. When the second length is greater than a value obtained by multiplying the first length by a first factor exceeding 1, a new boundary point is added to the line segment whereas when the second length is smaller than a value obtained by multiplying the first length by a second factor less than 1, one of the boundary points of the line segment is eliminated.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: December 27, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Kusunoki, Nobutoshi Aoki, Hirotaka Amakawa
  • Publication number: 20050205953
    Abstract: A semiconductor device includes a silicon substrate having a film thickness smaller than a maximum range of a particle generated by a nuclear reaction between a fast neutron and a silicon atom, and a semiconductor element formed on a surface of the silicon substrate.
    Type: Application
    Filed: June 24, 2004
    Publication date: September 22, 2005
    Inventors: Mitsutoshi Nakamura, Hirotaka Amakawa
  • Publication number: 20050184255
    Abstract: An ion implantation simulator that computes an ion density distribution at high speed and with high accuracy based on a beam dispersion phenomenon in an ion implantation process. The ion implantation simulator is provided with the beam dispersion approximate function storage section 121, which stores a beam dispersion approximate function that is obtained through approximation of ion beam dispersion by using a predetermined function; a beam intensity computing section 131, which computes an area surface beam intensity that indicates an intensity of the ion beam on a surface of an implanted area by using the beam dispersion approximate function; and an ion density distribution computing section 132, which computes the density distribution of the ion, which is implanted by the ion beam into the device through the surface of the implanted area, by using the area surface beam intensity.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 25, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Hirotaka Amakawa
  • Publication number: 20020087298
    Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 4, 2002
    Applicant: KABUSHHIKI KAISHA TOSHIBA
    Inventors: Sanae Ito, Hirotaka Amakawa
  • Publication number: 20010025233
    Abstract: Plural boundary points are generated on a string on the surface of a material and a first length of a line segment between the boundary points is obtained. Then, the displacement of the boundary point according to a process model and the boundary point is moved by the displacement. A second length of the line segment between the boundary points after the boundary point is moved is found. When the second length is greater than a value obtained by multiplying the first length by a first factor exceeding 1, a new boundary point is added to the line segment whereas when the second length is smaller than a value obtained by multiplying the first length by a second factor less than 1, one of the boundary points of the line segment is eliminated.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 27, 2001
    Inventors: Naoki Kusunoki, Nobuoshi Aoki, Hirotaka Amakawa
  • Patent number: 6099574
    Abstract: Process simulation for LSIs and other semiconductor devices will handle plural same impurities introduced in different processes as different impurities. Thus, by handling them as different impurities in calculation, it is possible to obtain the distribution profiles of impurities in semiconductor devices without being effected by another same impurity introduced in another process or a number of processes during processing. With this, even a plurality of process conditions are discussed or when one or some of process(es) in a sequence of semiconductor device fabrication processes is (are) changed in procedure, it is not necessary to repeat the process simulation many times from the beginning. And it is possible to easily decide which process must be changed in conditions based on a finally obtained structure of semiconductor devices.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: August 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sanae Fukuda, Hirotaka Amakawa, Takahisa Kanemura