Patents by Inventor Hirotaka Nishino

Hirotaka Nishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11114531
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 7, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masayasu Miyata, Hirotaka Nishino, Yoshihiko Moriyama, Yuichiro Mitani
  • Patent number: 10397139
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 27, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 10249718
    Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masayasu Miyata, Hirotaka Nishino, Yoshihiko Moriyama, Yuichiro Mitani
  • Publication number: 20180324111
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 8, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20180308936
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.
    Type: Application
    Filed: February 8, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Masayasu MIYATA, Hirotaka NISHINO, Yoshihiko MORIYAMA, Yuichiro MITANI
  • Publication number: 20180308935
    Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.
    Type: Application
    Filed: February 8, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Masayasu Miyata, Hirotaka Nishino, Yoshihiko Moriyama, Yuichiro Mitani
  • Patent number: 10044642
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20160149834
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: December 18, 2015
    Publication date: May 26, 2016
    Inventors: Kosuke TATSUMURA, Atsuhiro KINOSHITA, Hirotaka NISHINO, Masamichi SUZUKI, Yoshifumi NISHI, Takao MARUKAME, Takahiro KURITA
  • Patent number: 9246709
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 9083423
    Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Hirotaka Nishino, Kazuya Matsuzawa, Izumi Hirano, Takao Marukame, Yusuke Higashi, Takahiro Kurita, Yuki Sasaki, Yuichiro Mitani
  • Publication number: 20140227989
    Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.
    Type: Application
    Filed: December 17, 2013
    Publication date: August 14, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masamichi SUZUKI, Hirotaka NISHINO, Kazuya Matsuzawa, Izumi HIRANO, Takao MARUKAME, Yusuke HIGASHI, Takahiro KURITA, Yuki SASAKI, Yuichiro MITANI
  • Patent number: 8450208
    Abstract: In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki
  • Publication number: 20130069440
    Abstract: According to one embodiment, an incoming circuit using a magnetic resonant coupling includes an incoming coil which receives magnetic field energy transmitted from an outgoing coil under conditions of energy power transmission by the magnetic resonant coupling, and an incoming circuit which comprises a variable capacitor and a rectifier circuit and which outputs, as a direct-current voltage, the magnetic field energy received by the incoming coil. A capacitance of the variable capacitor is automatically controlled to change in an analog form along with the change of the direct-current voltage and to keep the transmission efficiency of the magnetic field energy at a fixed value by directly feeding back the direct-current voltage to the variable capacitor.
    Type: Application
    Filed: June 29, 2012
    Publication date: March 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Hirotaka NISHINO, Masamichi SUZUKI, Atsuhiro KINOSHITA
  • Publication number: 20120117354
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 10, 2012
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20120077341
    Abstract: In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
    Type: Application
    Filed: April 7, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki
  • Publication number: 20110254062
    Abstract: A field effect transistor which can operate at a low threshold value includes: an n-type semiconductor region; a source region and a drain region separately formed in the n-type semiconductor region; a first insulating film formed in the semiconductor region between the source region and the drain region and containing silicon and oxygen; a second insulating film formed on the first insulating film and containing at least one material selected from Hf, Zr, and Ti and oxygen; and a gate electrode formed on the second insulating film. Ge is doped in an interface region including an interface between the first insulating film and the second insulating film, and an area density of the Ge has a peak on a first insulating film side in the interface region.
    Type: Application
    Filed: March 8, 2011
    Publication date: October 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Atsuhiro Kinoshita, Hirotaka Nishino
  • Patent number: 7968933
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Patent number: 7863695
    Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Masato Koyama, Yoshinori Tsuchiya, Hirotaka Nishino, Reika Ichihara, Akira Takashima
  • Patent number: 7767538
    Abstract: It is made possible to form a silicon nitride film, an aluminum oxide film and a transition metal high-k insulation film of high quality. A manufacturing method includes: forming an insulation film having at least one kind of bonds selected out of silicon-nitrogen bonds, aluminum-oxygen bonds, transition metal-oxygen-silicon bonds, transition metal-oxygen-aluminum bonds, and transition metal-oxygen bonds on either a film having a semiconductor as a main component or a semiconductor substrate, and irradiating the insulation film with pulse infrared light having a wavelength corresponding to a maximum intensity in a wavelength region depending upon the insulation film and having a wavelength absorbed by the insulation film.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirotaka Nishino, Koichi Kato
  • Publication number: 20090236653
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 24, 2009
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino