Patents by Inventor Hirotaka Ogihara
Hirotaka Ogihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180264524Abstract: According to one embodiment, there is provided a template cleaning method. The method includes cleaning a template with a pattern formed on a surface, by using an acid or alkali. The method includes cleaning the template by using a cleaning liquid. The method includes rinsing the template by using a rinse liquid. The method includes performing an ashing process to the surface of the template by using a process gas. The cleaning liquid contains at least an auxiliary agent and a pH adjuster. The auxiliary agent contains grains made of a material that contains an organic substance as a main component.Type: ApplicationFiled: September 7, 2017Publication date: September 20, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yumi TANAKA, Kenji Iwade, Hirotaka Ogihara
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Patent number: 9905462Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.Type: GrantFiled: December 31, 2015Date of Patent: February 27, 2018Assignee: Toshiba Memory CorporationInventors: Atsuko Sakata, Takeshi Ishizaki, Shinya Okuda, Kei Watanabe, Masayuki Kitamura, Satoshi Wakatsuki, Daisuke Ikeno, Junichi Wada, Hirotaka Ogihara
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Patent number: 9780111Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.Type: GrantFiled: August 18, 2015Date of Patent: October 3, 2017Assignee: Toshiba Memory CorporationInventors: Takeshi Ishizaki, Junichi Wada, Atsuko Sakata, Kei Watanabe, Masayuki Kitamura, Daisuke Ikeno, Satoshi Wakatsuki, Hirotaka Ogihara, Shinya Okuda
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Patent number: 9779978Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.Type: GrantFiled: June 26, 2015Date of Patent: October 3, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
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Publication number: 20170053869Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.Type: ApplicationFiled: December 31, 2015Publication date: February 23, 2017Inventors: Atsuko SAKATA, Takeshi ISHIZAKI, Shinya OKUDA, Kei WATANABE, Masayuki KITAMURA, Satoshi WAKATSUKI, Daisuke IKENO, Junichi WADA, Hirotaka OGIHARA
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Publication number: 20160300845Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.Type: ApplicationFiled: August 18, 2015Publication date: October 13, 2016Inventors: Takeshi ISHIZAKI, Junichi WADA, Atsuko SAKATA, Kei WATANABE, Masayuki KITAMURA, Daisuke IKENO, Satoshi WAKATSUKl, Hirotaka OGIHARA, Shinya OKUDA
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Publication number: 20160276204Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.Type: ApplicationFiled: June 26, 2015Publication date: September 22, 2016Inventors: Atsuko SAKATA, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
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Publication number: 20160268283Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers; a first electrode layer included in the plurality of electrode layers; a second electrode layer included in the plurality of electrode layers; a first insulating layer provided between the first electrode layer and the second electrode layer, and provided in contact with the first electrode layer and the second electrode layer; a semiconductor portion; a charge storage film; a first conductive film; and second conductive film. The first conductive film is provided between the first electrode layer and the charge storage film, and provided in contact with the first insulating layer. The second conductive film is provided between the second electrode layer and the charge storage film, and provided in contact with the first insulating layer.Type: ApplicationFiled: July 9, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masayuki KITAMURA, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Junichi Wada, Kei Watanabe, Shinya Okuda, Hirotaka Ogihara, Hiroshi Nakazawa, Tomonori Aoyama, Kenji Aoyama, Hideaki Aochi
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Publication number: 20160064405Abstract: According to one embodiment, forming a metal film on an underlying layer, and depositing an oxide film on the metal film using plasma of a mixed gas induced above the metal film. The mixed gas includes a gaseous material source, a gaseous oxidant, and a gaseous reductant.Type: ApplicationFiled: January 30, 2015Publication date: March 3, 2016Inventors: SHINYA OKUDA, KEI WATANABE, HIROTAKA OGIHARA, MASAYUKI KITAMURA, TAKESHI ISHIZAKI, DAISUKE IKENO, SATOSHI WAKATSUKI, ATSUKO SAKATA, JUNICHI WADA
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Patent number: 8956982Abstract: According to one embodiment, a stacked film including at least a silicon oxide film is formed by stacking a plurality of films formed of different materials and a hard mask pattern is formed on the stacked film. Then, a stacked film pattern of a predetermined shape is formed by performing anisotropic etching on the stacked film by using the hard mask pattern as an etching mask and the hard mask pattern is removed. The hard mask pattern is formed by stacking at least one first hard mask layer and at least one second hard mask layer. The first hard mask layer is formed of a material having a higher removability in wet etching than the second hard mask layer. The first hard mask layer is arranged immediately above the stacked film.Type: GrantFiled: November 18, 2011Date of Patent: February 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Tsubata, Hirotaka Ogihara
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Patent number: 8796814Abstract: According to one embodiment, a semiconductor substrate device includes a plurality of memory elements formed on the top surface of a semiconductor substrate, interlayer insulating films buried between the adjacent memory elements, a protection film formed on sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements, and contacts formed in the interlayer insulating films. The protection film includes a first protection film formed on the sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements and a second protection film formed on the first protection film. The first protection film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the second protection film is made of a boron film or a boron nitride film.Type: GrantFiled: March 14, 2012Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Hirotaka Ogihara
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Patent number: 8742391Abstract: A non-volatile semiconductor memory includes a word line extending in a first direction, a first electrode connected to the word line electrically, an ion diffusion layer with connected to the first electrode electrically, a second electrode connected to the ion diffusion layer electrically and formed of a metal to be diffused into the ion diffusion layer when a positive voltage is supplied thereto, and a bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second electrode electrically. The ion diffusion layer has a first region disposed on the first electrode and a second region disposed between the first region and the second electrode, and the metal is more difficult to diffuse into the second region than into the first region.Type: GrantFiled: March 7, 2013Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Hirotaka Ogihara, Kensuke Takahashi, Masanobu Baba
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Publication number: 20130126995Abstract: According to one embodiment, a semiconductor substrate device includes a plurality of memory elements formed on the top surface of a semiconductor substrate, interlayer insulating films buried between the adjacent memory elements, a protection film formed on sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements, and contacts formed in the interlayer insulating films. The protection film includes a first protection film formed on the sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements and a second protection film formed on the first protection film. The first protection film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the second protection film is made of a boron film or a boron nitride film.Type: ApplicationFiled: March 14, 2012Publication date: May 23, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hirotaka Ogihara
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Publication number: 20120244712Abstract: According to one embodiment, a stacked film including at least a silicon oxide film is formed by stacking a plurality of films formed of different materials and a hard mask pattern is formed on the stacked film. Then, a stacked film pattern of a predetermined shape is formed by performing anisotropic etching on the stacked film by using the hard mask pattern as an etching mask and the hard mask pattern is removed. The hard mask pattern is formed by stacking at least one first hard mask layer and at least one second hard mask layer. The first hard mask layer is formed of a material having a higher removability in wet etching than the second hard mask layer. The first hard mask layer is arranged immediately above the stacked film.Type: ApplicationFiled: November 18, 2011Publication date: September 27, 2012Inventors: Shuichi TSUBATA, Hirotaka Ogihara
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Patent number: 7371654Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: GrantFiled: April 3, 2006Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Patent number: 7247888Abstract: There is here disclosed a film forming ring including a ring main body being made of an insulating material and formed in an annular shape along an edge of a substrate on which a film forming process by using a material gas in a plasma state is applied, and an inner rim of the ring main body being formed higher than its outside portion.Type: GrantFiled: February 28, 2005Date of Patent: July 24, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hirotaka Ogihara, Yukio Nishiyama, Akio Ui, Takashi O
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Publication number: 20060189092Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: ApplicationFiled: April 3, 2006Publication date: August 24, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Patent number: 7052971Abstract: A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.Type: GrantFiled: July 12, 2002Date of Patent: May 30, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Nishiyama, Hirotaka Ogihara, Rempei Nakata
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Publication number: 20050191811Abstract: There is here disclosed a film forming ring comprising a ring main body being made of an insulating material and formed in an annular shape along an edge of a substrate on which a film forming process by using a material gas in a plasma state is applied, and an inner rim of the ring main body being formed higher than its outside portion.Type: ApplicationFiled: February 28, 2005Publication date: September 1, 2005Inventors: Hirotaka Ogihara, Yukio Nishiyama, Akio Ui, Takashi O
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Patent number: 6798038Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: GrantFiled: May 9, 2002Date of Patent: September 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji