Abstract: A multilayer ceramic capacitor includes a ceramic body including a first internal electrode and a second internal electrode facing the first internal electrode, a pair of first external electrodes arranged on end surfaces of the ceramic body, respectively, connected to the first internal electrode; anda pair of second external electrodes arranged on side surfaces of the ceramic body, respectively, connected to the second internal electrode, wherein at least one of a first electrode main body portion and a second electrode main body portion has a first current regulating portion that is a cutout portion spaced apart from an outer edge of the corresponding first or second electrode main body portion and having a shape in which a ratio of a maximum longitudinal dimension to a maximum transverse dimension is greater than 1.

Abstract: A ceramic electronic device includes a multilayer structure having a substantially rectangular parallelepiped shape, a first cover layer, and a second cover layer that is provided on a second end of the multilayer structure in the stacking direction, a main component of the second cover layer being ceramic, a porosity of the second cover layer being higher than that of the first cover layer. Q=(A+B)/2C×100(%) is 0.5% or more and 1.6% or less, when, at an interface of the second cover layer on a side of the first cover layer, two heights of curvature portions of both ends of the interface are respectively a height A and a height B, and a shortest height from the first cover layer to the second cover layer is a height C.

Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).

Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).

Abstract: A power converter includes: a plurality of power modules that houses semiconductor elements for electric power conversion; a pair of holding plates sandwiching a stacked body of the plurality of power modules in the first direction; a pair of connecting beams that connects the pair of holding plates respectively on both side ends of the stacked body in the second direction intersecting the first direction; and a substrate connected to control terminals of the power modules. At least one of the pair of holding plates is provided with a positioner to position the substrate.

Abstract: A power converter includes: a plurality of power modules that houses semiconductor elements for electric power conversion; a pair of holding plates sandwiching a stacked body of the plurality of power modules in the first direction; a pair of connecting beams that connects the pair of holding plates respectively on both side ends of the stacked body in the second direction intersecting the first direction; and a substrate connected to control terminals of the power modules. At least one of the pair of holding plates is provided with a positioner to position the substrate.

Abstract: A power converter includes: a plurality of power modules that houses semiconductor elements for electric power conversion; a pair of holding plates sandwiching a stacked body of the plurality of power modules in the first direction; a pair of connecting beams that connects the pair of holding plates respectively on both side ends of the stacked body in the second direction intersecting the first direction; and a substrate connected to control terminals of the power modules. At least one of the pair of holding plates is provided with a positioner to position the substrate.

Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).

Abstract: A semiconductor device that is capable of suitably dissipating heat from a semiconductor chip is proposed. The proposed semiconductor device may include a semiconductor chip provided with a semiconductor substrate and a surface electrode provided on a surface of the semiconductor substrate; and a conductive plate provided with a plate shape portion and a convex portion protruding from the plate shape portion. An end surface of the convex portion may be corrected to the surface electrode. A width of the end surface of the convex portion may be narrower than a width of a base portion of the convex portion on a plate shape portion side.

Abstract: A method of manufacturing a semiconductor device by connecting a semiconductor chip to a lead frame using a jig, the semiconductor chip including a main electrode provided at a surface of the semiconductor chip, the lead frame including a connection projecting portion and a positioning portion, the positioning portion including at least one of a convex shape and a concave shape provided around the connection projecting portion, the method may include: engaging the jig to the positioning portion in a state where a clearance is provided between the connection projecting portion and the jig; engaging the jig to the semiconductor chip; and connecting the connection projecting portion to the main electrode of the semiconductor chip via solder in a state where the jig is engaged to the positioning portion and the semiconductor chip.

Abstract: A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device comprises: first sealing resin; first-third terminals; a first semiconductor chip connected to the first and third terminals. Each second semiconductor device comprises: second sealing resin; fourth-sixth terminals; a second semiconductor chip connected to the fourth and fifth terminals, and not connected to the sixth terminal. The first and second semiconductor devices are stacked along a stacking direction. The first terminals and the fourth terminals are arranged in a line along the stacking direction. The second terminals and the fifth terminals are arranged in a line along the stacking direction. The third terminals and the sixth terminals are arranged in a line along the stacking direction. The first wire is connected to the fifth terminals. The second wire is connected to the third terminals.

Abstract: In a power converter, a plurality of semiconductor devices and a plurality of cooling plates are stacked. The plurality of semiconductor devices includes a first-first sealed semiconductor device, a second-first sealed semiconductor device, and a plurality of second sealed semiconductor devices. The first-first sealed semiconductor device has a first high potential side terminal, and a first low potential side terminal. The second-first sealed semiconductor device has a second high potential side terminal, and a second low potential side terminal. When viewed along a stacking direction, the first high potential side terminal is disposed to overlap with the second low potential side terminal.

Abstract: In a power converter, a plurality of semiconductor devices and a plurality of cooling plates are stacked. The plurality of semiconductor devices includes a first-first sealed semiconductor device, a second-first sealed semiconductor device, and a plurality of second sealed semiconductor devices. The first-first sealed semiconductor device has a first high potential side terminal, and a first low potential side terminal. The second-first sealed semiconductor device has a second high potential side terminal, and a second low potential side terminal. When viewed along a stacking direction, the first high potential side terminal is disposed to overlap with the second low potential side terminal.

Abstract: A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device comprises: first sealing resin; first-third terminals; a first semiconductor chip connected to the first and third terminals. Each second semiconductor device comprises: second sealing resin; fourth-sixth terminals; a second semiconductor chip connected to the fourth and fifth terminals, and not connected to the sixth terminal. The first and second semiconductor devices are stacked along a stacking direction. The first terminals and the fourth terminals are arranged in a line along the stacking direction. The second terminals and the fifth terminals are arranged in a line along the stacking direction. The third terminals and the sixth terminals are arranged in a line along the stacking direction. The first wire is connected to the fifth terminals. The second wire is connected to the third terminals.

Abstract: This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices.

Abstract: A semiconductor device of the present invention has a purpose to form a structure of preventing outflow of solder at low costs. A semiconductor element is bonded to a substrate through a solder layer. An outflow-preventing part is provided to surround the solder layer to prevent solder outflow during soldering. The outflow-preventing part is formed by a cold spray method and has a surface in an oxidized state.

Abstract: A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween.

Abstract: This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices.

Abstract: A purpose of the application is to provide a semiconductor device production method capable of reducing complexity of production operations and keeping production costs low, and enhancing reliability, and a semiconductor device. One aspect of the invention provides a method of producing a semiconductor device, the method including a first bonding step of bonding a first electrode plate and a semiconductor device portion, and a second bonding step of bonding the semiconductor device portion and a second electrode plate. The method includes a sealing step of forming a sealed composite body by covering target surfaces of a composite body formed by the first bonding step with resin, the target surfaces being surfaces other than a second surface of the first electrode plate and the second surface of the semiconductor device portion. The second bonding step is performed after the sealing step.

Abstract: Disclosed is a semiconductor device wherein the adhesion of resin to a substrate is improved at a low cost. A semiconductor element and one or two substrates opposing one or both of the surfaces of the semiconductor element are sealed by a resin, a resin bonding coat which is formed by spraying a metal powder by a cold spray method is formed on one or both of the substrates, and recess portions which are widened from a film surface in a depth direction are formed on the resin bonding coat.