Patents by Inventor Hirotaka Tsuda
Hirotaka Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978660Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.Type: GrantFiled: June 7, 2023Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventor: Hirotaka Tsuda
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Publication number: 20230418155Abstract: A template includes a first region having a first face on a side opposite to a main face and a first pattern including a convex-concave portion provided on the first face, and a second region, provided around the first region, having a second face on the side opposite to the main face, a second pattern including a protruding portion protruding from the second face, and an optical layer provided on the second face and the second pattern, wherein the second face is positioned farther to the main surface side than a bottommost face of the irregular portion.Type: ApplicationFiled: February 22, 2023Publication date: December 28, 2023Applicant: Kioxia CorporationInventor: Hirotaka TSUDA
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Publication number: 20230354610Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Applicant: Kioxia CorporationInventors: Hirotaka TSUDA, Yusuke OSHIKI
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Publication number: 20230317515Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventor: Hirotaka TSUDA
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Patent number: 11744074Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: April 7, 2022Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Patent number: 11728210Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.Type: GrantFiled: February 26, 2021Date of Patent: August 15, 2023Assignee: Kioxia CorporationInventor: Hirotaka Tsuda
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Publication number: 20220293617Abstract: A semiconductor storage device includes a first conductive layer extending in a first direction; a second conductive layer arranged apart from the first conductive layer in a second direction intersecting the first direction, and extending in the first direction; a plurality of semiconductor layers provided between the first conductive layer and the second conductive layer, arranged in the first direction, and including a first region facing the first conductive layer, a second region facing the second conductive layer, a third region connected to one end of the first region in the first direction and one end of the second region in the first direction, and a fourth region connected to the other end of the first region in the first direction and the other end of the second region in the first direction; a plurality of first memory cells provided between the first conductive layer and the plurality of semiconductor layers, respectively; and a plurality of second memory cells provided between the second conductType: ApplicationFiled: August 31, 2021Publication date: September 15, 2022Applicant: Kioxia CorporationInventor: Hirotaka TSUDA
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Publication number: 20220231045Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Applicant: Kioxia CorporationInventors: Hirotaka TSUDA, Yusuke OSHIKI
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Patent number: 11322513Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: February 4, 2020Date of Patent: May 3, 2022Assignee: Kioxia CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20220080650Abstract: An imprint device of an embodiment includes an imaging device and a controller. The controller acquires, from the imaging device, a reference image which is a captured image of the template before the imprint operation at a predetermined imprint position and an imprint image which is a captured image of the template during the imprint operation at the imprint position. The control unit acquires features based on interference fringes appearing on the template during the imprint operation from a difference image representing a difference between the reference image and the imprint image. The control unit performs processes for controlling the imprint operation based on the features.Type: ApplicationFiled: March 11, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventor: Hirotaka TSUDA
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Publication number: 20210287935Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate maybe used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.Type: ApplicationFiled: February 26, 2021Publication date: September 16, 2021Inventor: Hirotaka TSUDA
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Publication number: 20210016473Abstract: An imprinting method includes capturing an image of a resin layer formed on a region of a first substrate with resin fluid supplied onto the first substrate from a resin fluid dispenser, determining a luminance distribution in the region in the captured image, determining a thickness distribution of the resin layer based on a relationship between a thickness of a resin layer and a luminance and the determined luminance distribution, determining a resin fluid supply condition to form a resin layer in a predetermined thickness range, based on the determined thickness distribution, and supplying resin fluid from the resin fluid dispenser onto a region of a second substrate in accordance with the determined resin fluid supply condition.Type: ApplicationFiled: February 28, 2020Publication date: January 21, 2021Inventor: Hirotaka TSUDA
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Publication number: 20200176469Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hirotaka TSUDA, Yusuke Oshiki
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Patent number: 10593694Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: October 17, 2018Date of Patent: March 17, 2020Assignee: Toshiba Memory CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20190051663Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Applicant: Toshiba Memory CorporationInventors: Hirotaka TSUDA, Yusuke Oshiki
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Patent number: 10141329Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: February 23, 2017Date of Patent: November 27, 2018Assignee: Toshiba Memory CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20170162596Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: February 23, 2017Publication date: June 8, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hirotaka TSUDA, Yusuke OSHIKI
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Patent number: 9627401Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: March 4, 2015Date of Patent: April 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20160126252Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: March 4, 2015Publication date: May 5, 2016Inventors: Hirotaka TSUDA, Yusuke OSHIKI
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Publication number: 20150363516Abstract: In one embodiment, a topography simulation apparatus includes a division module configured to divide topography of a substance of a semiconductor device into first to n-th layers, where n is an integer of two or more. The apparatus further includes a flux calculation module configured to calculate, for each of the first to n-th layers, a flux of particles which reach a surface of the substance in each layer. The apparatus further includes a topography calculation module configured to calculate, for each of the first to n-th layers, an amount of change of the topography of the substance in each layer based on the flux.Type: ApplicationFiled: September 10, 2014Publication date: December 17, 2015Inventors: Hirotaka TSUDA, Masanori TAKAHASHI