Patents by Inventor Hirotaka Tsuda

Hirotaka Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978660
    Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventor: Hirotaka Tsuda
  • Publication number: 20230418155
    Abstract: A template includes a first region having a first face on a side opposite to a main face and a first pattern including a convex-concave portion provided on the first face, and a second region, provided around the first region, having a second face on the side opposite to the main face, a second pattern including a protruding portion protruding from the second face, and an optical layer provided on the second face and the second pattern, wherein the second face is positioned farther to the main surface side than a bottommost face of the irregular portion.
    Type: Application
    Filed: February 22, 2023
    Publication date: December 28, 2023
    Applicant: Kioxia Corporation
    Inventor: Hirotaka TSUDA
  • Publication number: 20230354610
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Applicant: Kioxia Corporation
    Inventors: Hirotaka TSUDA, Yusuke OSHIKI
  • Publication number: 20230317515
    Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventor: Hirotaka TSUDA
  • Patent number: 11744074
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Patent number: 11728210
    Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventor: Hirotaka Tsuda
  • Publication number: 20220293617
    Abstract: A semiconductor storage device includes a first conductive layer extending in a first direction; a second conductive layer arranged apart from the first conductive layer in a second direction intersecting the first direction, and extending in the first direction; a plurality of semiconductor layers provided between the first conductive layer and the second conductive layer, arranged in the first direction, and including a first region facing the first conductive layer, a second region facing the second conductive layer, a third region connected to one end of the first region in the first direction and one end of the second region in the first direction, and a fourth region connected to the other end of the first region in the first direction and the other end of the second region in the first direction; a plurality of first memory cells provided between the first conductive layer and the plurality of semiconductor layers, respectively; and a plurality of second memory cells provided between the second conduct
    Type: Application
    Filed: August 31, 2021
    Publication date: September 15, 2022
    Applicant: Kioxia Corporation
    Inventor: Hirotaka TSUDA
  • Publication number: 20220231045
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: Kioxia Corporation
    Inventors: Hirotaka TSUDA, Yusuke OSHIKI
  • Patent number: 11322513
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Publication number: 20220080650
    Abstract: An imprint device of an embodiment includes an imaging device and a controller. The controller acquires, from the imaging device, a reference image which is a captured image of the template before the imprint operation at a predetermined imprint position and an imprint image which is a captured image of the template during the imprint operation at the imprint position. The control unit acquires features based on interference fringes appearing on the template during the imprint operation from a difference image representing a difference between the reference image and the imprint image. The control unit performs processes for controlling the imprint operation based on the features.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventor: Hirotaka TSUDA
  • Publication number: 20210287935
    Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate maybe used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 16, 2021
    Inventor: Hirotaka TSUDA
  • Publication number: 20210016473
    Abstract: An imprinting method includes capturing an image of a resin layer formed on a region of a first substrate with resin fluid supplied onto the first substrate from a resin fluid dispenser, determining a luminance distribution in the region in the captured image, determining a thickness distribution of the resin layer based on a relationship between a thickness of a resin layer and a luminance and the determined luminance distribution, determining a resin fluid supply condition to form a resin layer in a predetermined thickness range, based on the determined thickness distribution, and supplying resin fluid from the resin fluid dispenser onto a region of a second substrate in accordance with the determined resin fluid supply condition.
    Type: Application
    Filed: February 28, 2020
    Publication date: January 21, 2021
    Inventor: Hirotaka TSUDA
  • Publication number: 20200176469
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hirotaka TSUDA, Yusuke Oshiki
  • Patent number: 10593694
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Publication number: 20190051663
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hirotaka TSUDA, Yusuke Oshiki
  • Patent number: 10141329
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Publication number: 20170162596
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 8, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirotaka TSUDA, Yusuke OSHIKI
  • Patent number: 9627401
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirotaka Tsuda, Yusuke Oshiki
  • Publication number: 20160126252
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
    Type: Application
    Filed: March 4, 2015
    Publication date: May 5, 2016
    Inventors: Hirotaka TSUDA, Yusuke OSHIKI
  • Publication number: 20150363516
    Abstract: In one embodiment, a topography simulation apparatus includes a division module configured to divide topography of a substance of a semiconductor device into first to n-th layers, where n is an integer of two or more. The apparatus further includes a flux calculation module configured to calculate, for each of the first to n-th layers, a flux of particles which reach a surface of the substance in each layer. The apparatus further includes a topography calculation module configured to calculate, for each of the first to n-th layers, an amount of change of the topography of the substance in each layer based on the flux.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 17, 2015
    Inventors: Hirotaka TSUDA, Masanori TAKAHASHI