Abstract: A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. The one or more first buffers of one of the signal buses are different in number from the one or more first buffers of a different one of the signal buses.

Abstract: A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. The one or more first buffers of one of the signal buses are different in number from the one or more first buffers of a different one of the signal buses.

Abstract: A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal.

Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.

Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.

Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.

Abstract: An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.

Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.

Abstract: A semiconductor device includes first, second and third terminals respectively receiving first, second and third input signals from outside, first, second and third input buffers respectively coupled to the first, second and third terminals, the first, second and third input buffers producing first, second and third buffered signals responsive to the first, second and third input signals, respectively, and first and second gate circuits respectively coupled to the first and second input buffers, the first and second gate circuits coupled to the third input buffer in common, the first and second gate circuits respectively driving output nodes thereof in response to the first and second buffered signals when the third buffered signal is activated, and each of the first and second gate circuits holding the output nodes thereof at a fixed level irrelatively to the first and second buffered signals when the third buffered signal is inactivated.

Abstract: A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed.

Abstract: A semiconductor device includes first, second and third terminals respectively receiving first, second and third input signals from outside, first, second and third input buffers respectively coupled to the first, second and third terminals, the first, second and third input buffers producing first, second and third buffered signals responsive to the first, second and third input signals, respectively, and first and second gate circuits respectively coupled to the first and second input buffers, the first and second gate circuits coupled to the third input buffer in common, the first and second gate circuits respectively driving output nodes thereof in response to the first and second buffered signals when the third buffered signal is activated, and each of the first and second gate circuits holding the output nodes thereof at a fixed level irrelatively to the first and second buffered signals when the third buffered signal is inactivated.

Abstract: A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed.

Abstract: A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits for sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed.

Abstract: A synchronous semiconductor device includes: input buffers; a latch-signal generating circuit that generates a latch signal based on a clock signal; latch circuits that latch an address signal in response to the latch signal; delay circuits that supply the latch circuits with the address signal in synchronism with the latch signal; NOR gate circuits that inactivate the address signal in response to a chip select signal becoming inactive, the NOR gate circuits being arranged between the input buffers and the delay circuits. According to the present invention, without stopping an operation of the input buffers or an internal clock signal, consumed power generated between the input buffers and the latch circuits can be effectively reduced.

Abstract: A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits for sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed.

Abstract: A synchronous semiconductor device includes: input buffers; a latch-signal generating circuit that generates a latch signal based on a clock signal; latch circuits that latch an address signal in response to the latch signal; delay circuits that supply the latch circuits with the address signal in synchronism with the latch signal; NOR gate circuits that inactivate the address signal in response to a chip select signal becoming inactive, the NOR gate circuits being arranged between the input buffers and the delay circuits. According to the present invention, without stopping an operation of the input buffers or an internal clock signal, consumed power generated between the input buffers and the latch circuits can be effectively reduced.

Abstract: An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.