Patents by Inventor Hiroto Kodama

Hiroto Kodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966669
    Abstract: A molten metal component estimation device including: an input device configured to receive measurement information about a refining facility including measurement results regarding an optical characteristic; a model database that stores model expressions and model parameters, regarding a blowing process reaction, including a model expression and model parameters representing a relation between the oxygen efficiency in decarburization and a carbon concentration in a molten metal in the refining facility; and a processor configured to: estimate component concentrations of the molten metal including the carbon concentration in the molten metal by using the measurement information, the model expressions and the model parameters; estimate the carbon concentration in the molten metal based on the measurement results; and determine the model expression and the model parameters to be used when estimating the component concentrations of the molten metal, based on the estimation result of the carbon concentration in t
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 23, 2024
    Assignee: JFE STEEL CORPORATION
    Inventors: Hiroto Kase, Shinji Tomiyama, Yukio Takahashi, Shota Amano, Toshifumi Kodama
  • Patent number: 10461766
    Abstract: A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroto Kodama, Masaki Kudo, Takeshi Kusunoki
  • Publication number: 20190068211
    Abstract: A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 28, 2019
    Inventors: Hiroto KODAMA, Masaki KUDO, Takeshi KUSUNOKI
  • Patent number: 8890503
    Abstract: A power supply has first and second reference voltage sources; a step-down voltage generator, including a transistor supplied with a first voltage, a resistor string between the transistor and a second voltage, and an op-amp which controls the transistor, and outputting the voltage at a first node among nodes in the resistor string; switches, coupled to the nodes; a comparison circuit, which compares the voltage at a common node the switches coupling in common with the second reference voltage source; and a calibration control circuit, which selects any switch according to a comparison result to calibrate. During calibration, the calibration control circuit couples a second node among the nodes to a non-inverting terminal of the op-amp, and the first reference voltage source to an inverting terminal of the op-amp, and after calibration, couples the common node to the non-inverting terminal, and the second reference voltage source to the inverting terminal.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroto Kodama, Akimitsu Tajima, Hideaki Kondo, Osamu Moriwaki