Patents by Inventor Hiroto Matsubayashi

Hiroto Matsubayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11215639
    Abstract: A probe card has an edge sensor. The edge sensor has a first needle and a second needle. The first needle and the second needle are in contact with each other when the first needle and a wafer are not in contact with each other, and the first needle and the second needle are not in contact with each other when the first needle and the wafer are in contact with each other. The probe card has a resistor connected between the first needle and the second needle.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroto Matsubayashi, Takayuki Matsumoto, Tomoaki Nakamura
  • Publication number: 20210140998
    Abstract: A probe card has an edge sensor. The edge sensor has a first needle and a second needle. The first needle and the second needle are in contact with each other when the first needle and a wafer are not in contact with each other, and the first needle and the second needle are not in contact with each other when the first needle and the wafer are in contact with each other. The probe card has a resistor connected between the first needle and the second needle.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 13, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroto MATSUBAYASHI, Takayuki MATSUMOTO, Tomoaki NAKAMURA
  • Patent number: 5905384
    Abstract: An apparatus of testing a semiconductor element applies pulsed voltages synchronized with each other, respectively, to a gate and a drain of a semiconductor element being tested and measures current flowing through the semiconductor element in response to the pulsed voltages thus applied. The testing apparatus produces pulsed I-V characteristics considering the influences of self heating and surface energy levels of the semiconductor element and RF swing along a load line during large signal operation.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: May 18, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Inoue, Yasuharu Nakajima, Yukio Ohta, Hiroto Matsubayashi
  • Patent number: 5801528
    Abstract: A semiconductor element evaluating apparatus for evaluating an electrical characteristic of a semiconductor element used in a microwave band includes a pedestal having first and second waveguide parts for exchanging signals with external devices and penetrating the pedestal, a mode converting carrier member placed on the pedestal and having first and second waveguide parts and first and second microstrip lines sandwiching a region where a semiconductor element is to be mounted, and waveguide terminal structures placed on the mode converting carrier member. The first and second waveguide parts of the pedestal, the mode converting carrier member, and the terminal parts form first and second waveguides. One semiconductor element can be exchanged for another semiconductor element merely by exchanging one mode converting carrier member for another, and the length of the transmission line is shortened whereby transmission loss is reduced.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: September 1, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takayuki Katoh, Hiroto Matsubayashi
  • Patent number: 5786627
    Abstract: An integrated circuit device includes a substrate, circuit elements on the substrate, and an electrically conductive thermoplastic resin substance electrically connecting the circuit elements on the substrate. Therefore, since variations in the configuration of the thermoplastic resin are quite small relative to those of interconnecting wires, variation in parasitic inductance due to variation in the configuration of the connections is reduced and the uniformity and the reproducibility of the high frequency characteristics of the integrated circuit device are enhanced. A method for fabricating an integrated circuit device includes forming circuit elements on a substrate and forming an electrically conducting thermoplastic resin substance electrically connecting the circuit elements.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: July 28, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Inoue, Kei Goto, Yoshihiro Notani, Yasuharu Nakajima, Hiroto Matsubayashi, Yukio Ohta
  • Patent number: 5675184
    Abstract: An integrated circuit device includes a substrate; circuit elements including an active element and a bias line for applying a DC bias voltage to the active element, disposed on the substrate; a thermoplastic material layer disposed on a region of the substrate; and a magnetic substance layer disposed on a region of the substrate including a region of the bias line, and adhered to and supported by the thermoplastic material layer. In this structure, the magnetic substance layer can be formed in an appropriate shape and at an appropriate position on the bias line according to the oscillation characteristics of the active element, such as a transistor, and the magnetic substance layer absorbs the frequency components of the oscillation of the active element, whereby oscillation of the active element is easily prevented.
    Type: Grant
    Filed: January 17, 1996
    Date of Patent: October 7, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroto Matsubayashi, Kei Goto, Yoshihiro Notani, Yukio Ohta, Akira Inoue, Yasuharu Nakajima
  • Patent number: 5426399
    Abstract: A film carrier signal transmission line includes a dielectric material having a first, front surface and a second, rear surface opposite the first surface, signal lines buried in the dielectric material for transmitting a super high frequency signal, spaced from the first and second surfaces, and spaced side-by-side at a regular interval; a first grounding film disposed on the second surface of the dielectric material; separating grooves in the dielectric material between adjacent pairs of signal lines, parallel to the signal lines; and second grounding films disposed on the first surface of the dielectric material and in the separating grooves and electrically connected with said first grounding film in the separating grooves. Adjacent signal lines are electrically shielded and crosstalk between signal lines is reduced.
    Type: Grant
    Filed: December 13, 1993
    Date of Patent: June 20, 1995
    Inventors: Hiroto Matsubayashi, Yasuharu Nakajima, Yoshihiro Notani
  • Patent number: 5412235
    Abstract: In a semiconductor integrated circuit, an amplifier FET and a gate bias FET, having the same structure as the amplifier FET and a total gate width smaller than that of the amplifier FET, are disposed close to each other. The gate bias FET is a constituent of a gate bias circuit for the amplifier FET, and the current determined by the drain current of the gate bias FET, first and second resistors respectively connected to drain and source of the gate bias FET, and a diode connected in series to the first resistor is applied to the amplifier FET as a gate bias voltage. In this structure, if the DC characteristic of the amplifier FET varies from chip to chip, the DC characteristic of the gate bias FET formed in the vicinity of and simultaneously with the amplifier FET also varies.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: May 2, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuharu Nakajima, Hiroto Matsubayashi