Abstract: A semiconductor integrated circuit includes a first and second power supply domain circuits having a first and second power supply terminals, respectively. An internal signal propagation line propagates a signal from a circuit of the first power supply domain circuit to that of the second power supply domain circuit. A voltage detector detects a surge voltage input to the first and second power supply terminals and outputs, from a control signal node, a control signal which is determined in accordance with a capacitive coupling by a first capacitor between the first power supply terminal and the control signal node, a second capacitor between the second power supply terminal and the control signal node, and a load capacitance at an output side of the control signal node. A voltage limiting circuit limits a voltage of a signal on the internal signal propagation line in accordance with the control signal.

Abstract: A plurality of reference voltages are generated by a reference voltage generation circuit. A plurality of comparators is supplied respectively with an analog input voltage and any two reference voltages out of the plurality of reference voltages. A threshold voltage of each of the comparators is adjusted according to the two reference voltages. Each of the comparators compares the analog input voltage with the threshold voltage. A plurality of comparison output signals of the plurality of comparators are supplied to an encoder circuit, and digital signals which correspond to the plurality of comparison output signals are output.

Abstract: An A/D converter has a first voltage generation circuit, a second voltage generation circuit, a comparator, first and second switch circuits connected in series between an input terminal of an analog input voltage and an output terminal of the first voltage generation circuit, a first capacitor inserted between a connection node between the first and second switch circuits and the first input terminal, a second capacitor inserted between an output terminal of the second voltage generation circuit and the second input terminal, a third switch circuit, a fourth switch circuit, an A/D converter which generates a digital signal in accordance with signal level of the first output terminal, and a voltage setting circuit which sets a voltage to be outputted from the first and second voltage generation circuits based on the digital signal.

Abstract: First and second analog switches are connected in series between first and second nodes. One terminal of a third analog switch is connected to a series connection node of the first and second analog switches. The other terminal of the third analog switch is supplied with a second voltage different from a first voltage applied to the first node. The third analog switch drives on when the first and second analog switches drive off, and outputs the second voltage to the series connection node of the first and second analog switches.

Abstract: A semiconductor integrated circuit device is disclosed, which comprises power supply system circuits, in which power supply terminals and/or ground terminals are separated from each other between the power supply system circuits, an electrostatic discharge protecting circuit, an internal circuit provided in each of the power supply system circuits, an internal signal transmitting line, a surge input detecting circuit, and at least one of an input protecting circuit which is provided at an input side of the internal circuit and which limits a voltage of a signal transmitted from the internal signal transmitting line, and an output logic setting circuit which is provided at an output side of the internal circuit and which sets a logic level of a signal outputted to the internal signal transmitting line to a low level when the surge input detecting circuit has detected a surge input.

Abstract: A plurality of reference voltages are generated by a reference voltage generation circuit. A plurality of comparators is supplied respectively with an analog input voltage and any two reference voltages out of the plurality of reference voltages. A threshold voltage of each of the comparators is adjusted according to the two reference voltages. Each of the comparators compares the analog input voltage with the threshold voltage. A plurality of comparison output signals of the plurality of comparators are supplied to an encoder circuit, and digital signals which correspond to the plurality of comparison output signals are output.

Abstract: A plurality of reference voltages are generated by a reference voltage generation circuit. A plurality of comparators is supplied respectively with an analog input voltage and any two reference voltages out of the plurality of reference voltages. A threshold voltage of each of the comparators is adjusted according to the two reference voltages. Each of the comparators compares the analog input voltage with the threshold voltage. A plurality of comparison output signals of the plurality of comparators are supplied to an encoder circuit, and digital signals which correspond to the plurality of comparison output signals are output.

Abstract: An A/D converter has a first voltage generation circuit, a second voltage generation circuit, a comparator, first and second switch circuits connected in series between an input terminal of an analog input voltage and an output terminal of the first voltage generation circuit, a first capacitor inserted between a connection node between the first and second switch circuits and the first input terminal, a second capacitor inserted between an output terminal of the second voltage generation circuit and the second input terminal, a third switch circuit, a fourth switch circuit, an A/D converter which generates a digital signal in accordance with signal level of the first output terminal, and a voltage setting circuit which sets a voltage to be outputted from the first and second voltage generation circuits based on the digital signal.

Abstract: A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further includes a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal, and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

Abstract: A plurality of reference voltages are generated by a reference voltage generation circuit. A plurality of comparators is supplied respectively with an analog input voltage and any two reference voltages out of the plurality of reference voltages. A threshold voltage of each of the comparators is adjusted according to the two reference voltages. Each of the comparators compares the analog input voltage with the threshold voltage. A plurality of comparison output signals of the plurality of comparators are supplied to an encoder circuit, and digital signals which correspond to the plurality of comparison output signals are output.

Abstract: In an image processor, a memory device stores output inhibition conditions for inhibiting print of an image including a specified pattern. The input image data is converted to first image data for image forming. On the other hand, the input image data is also converted to second image data in correspondence to a state of a print obtained by the image output device, and a detector detects the specified pattern in the second image data based on the output inhibition conditions. Alternatively, a converter converts the output inhibition conditions to detection parameters according to output characteristics of the image output device, and a detector detects the specified pattern in the input image data based on the detection parameters. Then, a controller controls the output of the processed image data according to a result of the detection.

Abstract: In an image processor for detecting a circular pattern in an image, input image data is binarized to provide bi-level image data, and pixels having a predetermined value is counted in a block of a polygon having n vertices in the bi-level image data, wherein n denotes a natural number equal to or larger than eight. Then, it is decided, based on a number of the pixels having the predetermined value counted by the counter, whether the circular pattern is detected in the image or not. A detection window is used to detect the specified pattern. The detection window is moved successively by a predetermined number of pixels, in a direction from a side towards the center. The moving distance and direction are controlled based on the result of scan.

Abstract: In an image processor in a print system, an output device processes input data and outputs the processed data, while a detector detects whether data of a specified pattern is included in the input data or in the processed data, in parallel to the data processing by the output device. A stop controller makes the output device stop to output the processed data at an irregular timing after the detector detects the specified pattern. The printer prints an image on a sheet of paper, based on the data outputted by the output device. Thus when the specified pattern in an image is detected, the printing is stopped but the stop position becomes irregular.

Abstract: First and second analog switches are connected in series between first and second nodes. One terminal of a third analog switch is connected to a series connection node of the first and second analog switches. The other terminal of the third analog switch is supplied with a second voltage different from a first voltage applied to the first node. The third analog switch drives on when the first and second analog switches drive off, and outputs the second voltage to the series connection node of the first and second analog switches.

Abstract: A semiconductor integrated circuit device is disclosed, which comprises power supply system circuits, in which power supply terminals and/or ground terminals are separated from each other between the power supply system circuits, an electrostatic discharge protecting circuit, an internal circuit provided in each of the power supply system circuits, an internal signal transmitting line, a surge input detecting circuit, and at least one of an input protecting circuit which is provided at an input side of the internal circuit and which limits a voltage of a signal transmitted from the internal signal transmitting line, and an output logic setting circuit which is provided at an output side of the internal circuit and which sets a logic level of a signal outputted to the internal signal transmitting line to a low level when the surge input detecting circuit has detected a surge input.

Abstract: An image processor detects a specified pattern defined by arrangement of three or more elements. Positions of a plurality of element candidates are detected based on input image data, and n pairs (n?2) of element candidates are selected in the plurality of elements. Then, n arrangement criterions are determined based on the positions of the selected n pairs, and one arrangement criterion is determined based on the n arrangement criterions. By using the one arrangement criterion, positions of all the elements are calculated in the specified pattern. The specified pattern is detected based on the calculated positions of the arrangement.

Abstract: In a network printing system, initial print setting information and save-mode print setting information are preparatorily set as print setting information in a server. In response to a request from PC1 or PC2, the server sends the save-mode print setting information as the “print setting information” if the total number of print copies exceeds a predetermined number. If a user does not agree with the save-mode print setting information displayed on the PC1 or PC2, the user operates a button “no” in a confirmation dialogue and then resets the print setting information. A printing apparatus performs save-mode printing or normal printing in accordance with the set or reset print setting information. Therefore, an administrator of the network printing system has only to set the initial print setting information and the save-mode print setting information in the server. Thus, the network printing system allows print setting to be simply achieved.

Abstract: A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further includes a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal, and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

Abstract: A semiconductor device includes a first circuit block, the first circuit block having a first power supply terminal and a first ground terminal, a second circuit block, the second circuit block having a second power supply terminal and a second ground terminal, and a propagation circuit provided between an output terminal of the first circuit block and an input terminal of the second circuit block to propagate a signal. In the device, a signal input element connected to the input terminal of the second circuit block to which the signal is input through the propagation circuit has an input withstanding voltage which is higher than that of other elements of the second circuit block.

Abstract: Considering that MOS transistors on a common integrated circuit can be controlled in resistance ratio between them with a relatively high accuracy, a DA converter is improved in accuracy by replacing resistors required to be accurate with MOS transistors without inviting an increase of the chip area. That is, between a high potential reference voltage (VrefH) and a low potential reference voltage (VrefL), a plurality of MOS transistors (M1-MN) are connected in series such that they normally operate in a linear region and at least one turns OFF during power-down periods of the DA converter. One of partial voltages (V1-VN) of these MOS transistors (M1-MN) is selected by switches (SW1-SWN) controlled in ON-OFF motion by a control signal obtained by decoding a digital input (12) in a decoder (11), and delivered to an analog output (13), such that an analog value corresponding to the digital data given from the digital input (12) is sent out from the analog output 13.