Abstract: A load modulation circuit of an embodiment has a first element, a switch element configured to connect the first element to an end portion of a coil, a first control section configured to control an operation of the switch element, and a second control section configured to control an amount of electric charges accumulated in the first element, and the second control section discharges the electric charges accumulated in the first element when the switch element is switched to off.

Abstract: A rectification circuit connected to a coil and a capacitor, includes, on each terminal side of the coil, a high-side transistor connected between a terminal of the coil and the capacitor, first and second low-side transistors connected in parallel between the terminal of the coil and a fixed potential, a comparator that causes the first low-side transistor to be turned on when a voltage of the terminal of the coil decreases to a first value and then turned off when the voltage increases to a second value that is higher than the first value and lower than the fixed potential, and a controller that causes the second low-side transistor to be turned off when the voltage decreases to a third value that is higher than the second value and lower than the fixed potential, and then turned off when the voltage increases to the third value.

Abstract: The voltage regulator includes a resistor circuit that switches between a first state and a second state according to the comparison result signal. In the first state, a resistance between a second end of a first controlling transistor and a fixed potential is set at a first resistance, and a second end of a second controlling transistor and the fixed potential are disconnected from each other. In the second state, the second end of the first controlling transistor and the fixed potential are disconnected from each other, and a resistance between the second end of the second controlling transistor and the fixed potential is set at a second resistance.

Abstract: A load modulation circuit of an embodiment has a first element, a switch element configured to connect the first element to an end portion of a coil, a first control section configured to control an operation of the switch element, and a second control section configured to control an amount of electric charges accumulated in the first element, and the second control section discharges the electric charges accumulated in the first element when the switch element is switched to off.

Abstract: The voltage regulator includes a resistor circuit that switches between a first state and a second state according to the comparison result signal. In the first state, a resistance between a second end of a first controlling transistor and a fixed potential is set at a first resistance, and a second end of a second controlling transistor and the fixed potential are disconnected from each other. In the second state, the second end of the first controlling transistor and the fixed potential are disconnected from each other, and a resistance between the second end of the second controlling transistor and the fixed potential is set at a second resistance.

Abstract: A rectifying apparatus (power receiving apparatus) 100 is configured to receive electric power output from the power transmitting apparatus 101. The rectifying apparatus 100 is mobile equipment, such as a battery, a smartphone incorporating a battery and a tablet PC, or equipment for a battery charger connected to the equipment. The rectifying apparatus (power receiving apparatus) 100 may be any other equipment that receives electric power output from the associated power transmitting apparatus 101, including a rechargeable electric car, a household appliance and a product for underwater application.

Abstract: A power receiving unit includes a hysteresis comparator, includes a comparison voltage based on an output voltage at an output terminal and a first reference voltage and outputs a comparison result signal responsive to a result of the comparison. The power receiving unit includes a current operational amplifier that receives a converted voltage based on a current flowing through an output transistor and a preset second reference voltage and outputs a current error signal responsive to the difference between the converted voltage and the second reference voltage. The power receiving unit includes a first multiplexer that receives the current error signal and the comparison result signal, selects either of the comparison result signal and the current error signal based on the comparison result signal and outputs the selected signal. The output transistor is controlled based on a first output signal selected by the first multiplexer.

Abstract: According to one embodiment, an image processing device includes a defect correcting unit, a noise-reduction processing unit, and a selecting unit. The defect correcting unit executes defect correction on a target pixel. The defect correcting unit switches, according to the level of contrast determined concerning a plurality of peripheral pixels, a first correction value obtained through averaging processing for signal values of the peripheral pixels and a second correction value other than the first correction value.

Abstract: A rectifying apparatus (power receiving apparatus) 100 is configured to receive electric power output from the power transmitting apparatus 101. The rectifying apparatus 100 is mobile equipment, such as a battery, a smartphone incorporating a battery and a tablet PC, or equipment for a battery charger connected to the equipment. The rectifying apparatus (power receiving apparatus) 100 may be any other equipment that receives electric power output from the associated power transmitting apparatus 101, including a rechargeable electric car, a household appliance and a product for underwater application.

Abstract: The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.

Abstract: The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.

Abstract: To provide a three-dimensional Y/C separating circuit that has a high responsibility to a motion in a video signal and can reduce a memory capacity, a three-dimensional Y/C separating circuit has a 2-frame memory 14 that delays a color signal by an inversion period thereof to produce a delayed composite video signal, a luminance motion detecting part that produces a first frame correlation signal by a subtraction processing between the delayed composite video signal and a composite video signal, an adding circuit 23 that produces a mixed video signal by an addition processing between the delayed composite video signal and the composite video signal, a frame memory 24 that delays the mixed video signal by one frame period, a subtracting circuit 25 that produces a second frame correlation signal by a subtraction processing between the mixed video signal and the mixed video signal delayed by one frame period, a determining circuit 26 that determines a motion from the first and second frame correlation signals an

Abstract: A pixel-interpolation processing unit generates a sensitivity level value of an insufficient color component according to interpolation processing of image signals. A sensitivity level value of an insufficient color component in a pixel of attention is calculated, according to an arithmetic operation corresponding to an acquired color component of the pixel of attention, by assuming a geometric figure including sensitivity level values of acquired color components as vertexes. As the geometric figure, the same figure is used irrespectively of which color component the acquired color component is.

Abstract: According to one embodiment, an image processing device includes a defect correcting unit, a noise-reduction processing unit, and a selecting unit. The defect correcting unit executes defect correction on a target pixel. The defect correcting unit switches, according to the level of contrast determined concerning a plurality of peripheral pixels, a first correction value obtained through averaging processing for signal values of the peripheral pixels and a second correction value other than the first correction value.

Abstract: A pixel-interpolation processing unit generates a sensitivity level value of an insufficient color component according to interpolation processing of image signals. A sensitivity level value of an insufficient color component in a pixel of attention is calculated, according to an arithmetic operation corresponding to an acquired color component of the pixel of attention, by assuming a geometric figure including sensitivity level values of acquired color components as vertexes. As the geometric figure, the same figure is used irrespectively of which color component the acquired color component is.

Abstract: To provide a three-dimensional Y/C separating circuit that has a high responsibility to a motion in a video signal and can reduce a memory capacity, a three-dimensional Y/C separating circuit has a 2-frame memory 14 that delays a color signal by an inversion period thereof to produce a delayed composite video signal, a luminance motion detecting part that produces a first frame correlation signal by a subtraction processing between the delayed composite video signal and a composite video signal, an adding circuit 23 that produces a mixed video signal by an addition processing between the delayed composite video signal and the composite video signal, a frame memory 24 that delays the mixed video signal by one frame period, a subtracting circuit 25 that produces a second frame correlation signal by a subtraction processing between the mixed video signal and the mixed video signal delayed by one frame period, a determining circuit 26 that determines a motion from the first and second frame correlation signals an