Patents by Inventor Hiroto Shinoda

Hiroto Shinoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9577209
    Abstract: The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshifumi Tanada, Naoya Sakamoto, Hiroki Adachi, Shingo Eguchi, Koji Ono, Kensuke Yoshizumi, Hiroto Shinoda
  • Publication number: 20120205700
    Abstract: The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 16, 2012
    Inventors: Yoshifumi Tanada, Naoya Sakamoto, Hiroki Adachi, Shingo Eguchi, Koji Ono, Kensuke Yoshizumi, Hiroto Shinoda
  • Patent number: 7417241
    Abstract: An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the object of the invention is to provide an ion implantation method that can improve throughput during an ion implantation step of B and a method for manufacturing a semiconductor device. The ion implantation method comprises the steps of: introducing an impurity imparting p-type conductivity and H2O in an ion source; ionizing the impurity imparting p-type conductivity; and implanting into a semiconductor film.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: August 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Hiroto Shinoda
  • Publication number: 20070063147
    Abstract: According to the present invention, a manufacturing device of a semiconductor device provided with a device for uniformly doping with an impurity element a large area substrate capable of multiple patterns for the purpose of mass-production is provided. The present invention has a feature that a cross section of an ion current is to be a linear shape or a rectangle, and the large area substrate is moved in a direction perpendicular to a longitudinal direction of the ion current while keeping the large area substrate inclined at a predetermined tilt angle ? to the ion current. In this invention, an incident angle of an ion beam is adjusted as changing the tile angle ?. By making the large area substrate inclined to a horizontal plane, the width of the longitudinal direction of the ion current can be shortened than the length of a side of the substrate.
    Type: Application
    Filed: June 9, 2005
    Publication date: March 22, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Hiroto Shinoda, Osamu Nakamura, Atsuo Isobe, Tetsuji Yamaguchi, Hiromichi Godo
  • Publication number: 20060163494
    Abstract: An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the object of the invention is to provide an ion implantation method that can improve throughput during an ion implantation step of B and a method for manufacturing a semiconductor device. The ion implantation method comprises the steps of: introducing an impurity imparting p-type conductivity and H2O in an ion source; ionizing the impurity imparting p-type conductivity; and implanting into a semiconductor film.
    Type: Application
    Filed: December 28, 2005
    Publication date: July 27, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Hiroto Shinoda
  • Patent number: 6995079
    Abstract: An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the object of the invention is to provide an ion implantation method that can improve throughput during an ion implantation step of B and a method for manufacturing a semiconductor device. The ion implantation method comprises the steps of: introducing an impurity imparting p-type conductivity and H2O in an ion source; ionizing the impurity imparting p-type conductivity; and implanting into a semiconductor film.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: February 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Hiroto Shinoda
  • Publication number: 20050079694
    Abstract: An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the object of the invention is to provide an ion implantation method that can improve throughput during an ion implantation step of B and a method for manufacturing a semiconductor device. The ion implantation method comprises the steps of: introducing an impurity imparting p-type conductivity and H2O in an ion source; ionizing the impurity imparting p-type conductivity; and implanting into a semiconductor film.
    Type: Application
    Filed: August 27, 2004
    Publication date: April 14, 2005
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Junichi Koezuka, Hiroto Shinoda