Abstract: According to one embodiment, a memory system includes: a plurality of memory chips; a plurality of memory controllers; and a data encoding circuit configured to form a first group including a continuous plurality of first divided data among the user data, and generate a plurality of first page data. The memory controllers adjust a schedule of a write operation among the memory controllers and control a number of the write operations to be simultaneously executed. When at least one of the memory chips is in a busy state in a first read request, the memory controller connected to the memory chip in the busy state decodes the first divided data through erasure correction decoding processing using the first divided data read from the memory chip not in the busy state.

Abstract: A storage system is provided, including: a host including a memory, the memory including a submission queue and a completion queue and being configured to store update frequency information; and a memory system configured to be connectable with the host and including a nonvolatile memory and a controller, the controller configured to control the nonvolatile memory, to receive the update frequency information of the submission queue from the host, to read command information stored in the submission queue based on the received update frequency information, and to execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a memory system includes: a plurality of memory chips; a plurality of memory controllers; and a data encoding circuit configured to form a first group including a continuous plurality of first divided data among the user data, and generate a plurality of first page data. The memory controllers adjust a schedule of a write operation among the memory controllers and control a number of the write operations to be simultaneously executed. When at least one of the memory chips is in a busy state in a first read request, the memory controller connected to the memory chip in the busy state decodes the first divided data through erasure correction decoding processing using the first divided data read from the memory chip not in the busy state.

Abstract: A storage system is provided, including: a host including a memory, the memory including a submission queue and a completion queue and being configured to store update frequency information; and a memory system configured to be connectable with the host and including a nonvolatile memory and a controller, the controller configured to control the nonvolatile memory, to receive the update frequency information of the submission queue from the host, to read command information stored in the submission queue based on the received update frequency information, and to execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to be connectable with a host and control the nonvolatile memory. The controller is configured to receive update frequency information of a submission queue from the host, read command information stored in the submission queue in accordance with the update frequency information, and execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to be connectable with a host and control the nonvolatile memory. The controller is configured to receive update frequency information of a submission queue from the host, read command information stored in the submission queue in accordance with the update frequency information, and execute controlling for the nonvolatile memory based on the command information.

Abstract: A communication apparatus includes a deinterleaver and an error corrector. The deinterleaver sets, as an input, a third error-correction-code sequence obtained by rearranging bit positions of a second error-correction-code sequence in which two or more terminated first error-correction-code sequences are repeated from the terminated first error-correction-code sequences in accordance with a first rule. The deinterleaver rearranges bit positions of the third error-correction-code sequence in accordance with a second rule that is different from the first rule to configure a fourth error-correction-code sequence including one or more of the terminated first error-correction-code sequences. The error corrector performs error correction based on the fourth error-correction-code sequence. The second rule used by the deinterleaver is to extract bits capable of configuring the fourth error-correction-code sequence in order from a head of the third error-correction-code sequence.

Abstract: According to one embodiment, a power transmission and reception system includes a power transmitter and a power receiver. The power transmitter includes a power transmission module configured to wireless-transmit power to the power receiver; and a first wireless communication module configured to perform wireless communication of data frame having data with the power receiver. The power receiver includes a power reception module configured to receive the power transmitted from the power transmission module; and a second wireless communication module configured to perform wireless communication of the data frame with the first wireless communication module using the received power. The second wireless communication module is configured to perform wireless communication while the power reception module is not receiving the power.

Abstract: According to an embodiment, a wireless communication device includes a first wireless communication section, a wireless power receiving section and a wireless control section. The first wireless communication section is configured to transmit and receive a first wireless signal. The wireless power receiving section is configured to receive power by a second wireless signal. The wireless control section is configured to control the first wireless communication section according to a wireless power reception state of the wireless power receiving section. The wireless control section activates the first wireless communication section after wireless power reception by the wireless power receiving section is started.

Abstract: According to one embodiment, a power transmission and reception system includes a power transmitter and a power receiver. The power transmitter includes: a power transmission module configured to wireless-transmit power to the power receiver; and a first wireless communication module configured to perform wireless communication with the power receiver. The power receiver includes: a power reception module configured to receive the power transmitted from the power transmission module; and a second wireless communication module configured to perform wireless communication with the first wireless communication module using the received power. The second wireless communication module is configured to perform wireless communication while the power reception module is receiving the power.

Abstract: A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable generator is off, a second circuit whose output frequently changes, an input controller which receives the respective outputs from the second circuit and the Enable generator and passes through the input from the second circuit only when the output from the Enable generator is on, a combination circuit which receives the respective outputs from the first circuit and the input controller, and a memory which receives the output from the combination circuit and is driven by the output from the clock controller.

Abstract: According to one embodiment, a power transmission and reception system includes a power transmitter and a power receiver. The power transmitter includes: a power transmission module configured to wireless-transmit power to the power receiver; and a first wireless communication module configured to perform wireless communication with the power receiver. The power receiver includes: a power reception module configured to receive the power transmitted from the power transmission module; and a second wireless communication module configured to perform wireless communication with the first wireless communication module using the received power. The second wireless communication module is configured to perform wireless communication while the power reception module is receiving the power.

Abstract: According to one embodiment, a power transmission and reception system includes a power transmitter and a power receiver. The power transmitter includes a power transmission module configured to wireless-transmit power to the power receiver; and a first wireless communication module configured to perform wireless communication of data frame having data with the power receiver. The power receiver includes a power reception module configured to receive the power transmitted from the power transmission module; and a second wireless communication module configured to perform wireless communication of the data frame with the first wireless communication module using the received power. The second wireless communication module is configured to perform wireless communication while the power reception module is not receiving the power.

Abstract: According to an embodiment, a wireless communication device includes a first wireless communication section, a wireless power receiving section and a wireless control section. The first wireless communication section is configured to transmit and receive a first wireless signal. The wireless power receiving section is configured to receive power by a second wireless signal. The wireless control section is configured to control the first wireless communication section according to a wireless power reception state of the wireless power receiving section. The wireless control section activates the first wireless communication section after wireless power reception by the wireless power receiving section is started.

Abstract: There is provided a radio receiver including: a first matched filter, a second matched filter, a first frame synchronization determining unit and a first phase determining unit. The first matched filter performs matching processing on the basis of N first tap coefficients and sign information of a received digital signal to obtain first output data. The second matched filter performs matching processing on the basis of M (M is a natural number smaller than the N) second tap coefficients, the sign information and amplitude information of the received digital to obtain second output data. The first frame synchronization determining unit determines a first frame synchronization timing of the received digital signal on the basis of the first output data. The first phase determining unit determines a first phase amount of the received digital signal on the basis of the second output data and the first frame synchronization timing.

Abstract: According to one embodiment, a power source controller has a first power source line supplied with a reference power source voltage, a second power source line connected to an internal circuit, a control circuit configured to control a connection between the first power source line and the second power source line, a control signal line connected to the control circuit, and configured to provide a control signal for controlling the connection, a transistor comprising a first terminal, a second terminal and a control terminal in the control circuit, the control terminal of the transistor being connected to the control signal line, a semiconductor substrate on which the transistor is formed, and first through third wires.

Abstract: There is provided a radio receiver including: a first matched filter, a second matched filter, a first frame synchronization determining unit and a first phase determining unit. The first matched filter performs matching processing on the basis of N first tap coefficients and sign information of a received digital signal to obtain first output data. The second matched filter performs matching processing on the basis of M (M is a natural number smaller than the N) second tap coefficients, the sign information and amplitude information of the received digital to obtain second output data. The first frame synchronization determining unit determines a first frame synchronization timing of the received digital signal on the basis of the first output data. The first phase determining unit determines a first phase amount of the received digital signal on the basis of the second output data and the first frame synchronization timing.

Abstract: According to one embodiment, a power source controller has a first power source line supplied with a reference power source voltage, a second power source line connected to an internal circuit, a control circuit configured to control a connection between the first power source line and the second power source line, a control signal line connected to the control circuit, and configured to provide a control signal for controlling the connection, a transistor comprising a first terminal, a second terminal and a control terminal in the control circuit, the control terminal of the transistor being connected to the control signal line, a semiconductor substrate on which the transistor is formed, and first through third wires.

Abstract: A synchronizing circuit includes an internal partial power supply interruption circuit section which can be subjected to a power supply interruption and includes a data transmission register configured to output data for controlling a power supply interruption and a clock enable control register configured to output an enable signal; an internal partial power supply interruption control circuit section configured to control a power supply interruption and includes a gated clock buffer configured to control a clock signal based on the enable signal, and a data reception register configured to take in data based on the controlled clock signal; and an isolation cell configured to output an output from the internal partial power supply interruption circuit section as a fixed value when the internal partial power supply interruption circuit section has been subjected to a power supply interruption.

Abstract: A hardware engine control apparatus includes: a plurality of hardware engines (HWEs) connected by a control bus, each of the hardware engines executing a series of different kinds of processing; a host control device that outputs control commands for controlling operation of the HWEs to a subordinate control device; and the subordinate control device that has a register, in which the control commands from the host control device is sequentially set, and outputs the control commands set in the register to the control bus at timing based on a clock signal. The HWEs operate according to the control commands output from the subordinate control device.